Commit f67d0619 authored by danicampora's avatar danicampora
Browse files

cc3200: Fix SPI clock divider calculation.

parent d0601b0a
......@@ -782,15 +782,9 @@ SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk,
}
//
// Mask the configurations and set clock divider granularity
// to 1 cycle
// set clock divider granularity to 1 cycle
//
ulRegData = (ulRegData & (~(MCSPI_CH0CONF_WL_M |
MCSPI_CH0CONF_EPOL |
MCSPI_CH0CONF_POL |
MCSPI_CH0CONF_PHA |
MCSPI_CH0CONF_TURBO ) |
MCSPI_CH0CONF_CLKG));
ulRegData |= MCSPI_CH0CONF_CLKG;
//
// Get the divider value
......@@ -798,7 +792,7 @@ SPIConfigSetExpClk(unsigned long ulBase,unsigned long ulSPIClk,
ulDivider = ((ulSPIClk/ulBitRate) - 1);
//
// The least significant four bits of the divider is used fo configure
// The least significant four bits of the divider is used to configure
// CLKD in MCSPI_CHCONF next eight least significant bits are used to
// configure the EXTCLK in MCSPI_CHCTRL
//
......
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment