Commit e64032d6 authored by Tobias Badertscher's avatar Tobias Badertscher Committed by Damien George
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stmhal: L4: Adapt DMA to be able to support STM32L4 MCU series.

The main thing is to change the DMA code in a way that the structure
DMA_Stream_TypeDef (which is similar to DMA_Channel_TypeDef on stm32l4)
is no longer used outside of dma.c, as this structure only exists for the
F4 series.  Therefore I introduced a new structure (dma_descr_t) which
handles all DMA specific stuff for configuration.  Further the periphery
(spi, i2c, sdcard, dac) does not need to know the internals of the dma.
parent eb54e4d0
......@@ -67,7 +67,7 @@
/// dac = DAC(1)
/// dac.write_timed(buf, 400 * len(buf), mode=DAC.CIRCULAR)
#if MICROPY_HW_ENABLE_DAC
#if defined(MICROPY_HW_ENABLE_DAC) && MICROPY_HW_ENABLE_DAC
STATIC DAC_HandleTypeDef DAC_Handle;
......@@ -139,7 +139,7 @@ typedef enum {
typedef struct _pyb_dac_obj_t {
mp_obj_base_t base;
uint32_t dac_channel; // DAC_CHANNEL_1 or DAC_CHANNEL_2
DMA_Stream_TypeDef *dma_stream; // DMA1_Stream5 or DMA1_Stream6
const dma_descr_t *tx_dma_descr;
uint16_t pin; // GPIO_PIN_4 or GPIO_PIN_5
uint8_t bits; // 8 or 12
uint8_t state;
......@@ -162,7 +162,13 @@ STATIC mp_obj_t pyb_dac_init_helper(pyb_dac_obj_t *self, mp_uint_t n_args, const
HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
// DAC peripheral clock
#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
__DAC_CLK_ENABLE();
#elif defined(MCU_SERIES_L4)
__HAL_RCC_DAC1_CLK_ENABLE();
#else
#error Unsupported Processor
#endif
// stop anything already going on
HAL_DAC_Stop(&DAC_Handle, self->dac_channel);
......@@ -217,11 +223,11 @@ STATIC mp_obj_t pyb_dac_make_new(const mp_obj_type_t *type, mp_uint_t n_args, mp
if (dac_id == 1) {
dac->pin = GPIO_PIN_4;
dac->dac_channel = DAC_CHANNEL_1;
dac->dma_stream = DMA_STREAM_DAC1;
dac->tx_dma_descr = &dma_DAC_1_TX;
} else if (dac_id == 2) {
dac->pin = GPIO_PIN_5;
dac->dac_channel = DAC_CHANNEL_2;
dac->dma_stream = DMA_STREAM_DAC2;
dac->tx_dma_descr = &dma_DAC_2_TX;
} else {
nlr_raise(mp_obj_new_exception_msg_varg(&mp_type_ValueError, "DAC %d does not exist", dac_id));
}
......@@ -371,9 +377,12 @@ mp_obj_t pyb_dac_write_timed(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_
__DMA1_CLK_ENABLE();
DMA_HandleTypeDef DMA_Handle;
/* Get currently configured dma */
dma_init_handle(&DMA_Handle, self->tx_dma_descr, (void*)NULL);
/*
DMA_Cmd(self->dma_stream, DISABLE);
while (DMA_GetCmdStatus(self->dma_stream) != DISABLE) {
DMA_Cmd(DMA_Handle->Instance, DISABLE);
while (DMA_GetCmdStatus(DMA_Handle->Instance) != DISABLE) {
}
DAC_Cmd(self->dac_channel, DISABLE);
......@@ -389,18 +398,10 @@ mp_obj_t pyb_dac_write_timed(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_
DAC_Init(self->dac_channel, &DAC_InitStructure);
*/
// DMA1_Stream[67] channel7 configuration
DMA_HandleTypeDef DMA_Handle;
DMA_Handle.Instance = self->dma_stream;
// Need to deinit DMA first
DMA_Handle.State = HAL_DMA_STATE_READY;
HAL_DMA_DeInit(&DMA_Handle);
DMA_Handle.Init.Channel = DMA_CHANNEL_DAC1; // DAC1 & DAC2 both use the same channel
DMA_Handle.Init.Direction = DMA_MEMORY_TO_PERIPH;
DMA_Handle.Init.PeriphInc = DMA_PINC_DISABLE;
DMA_Handle.Init.MemInc = DMA_MINC_ENABLE;
if (self->bits == 8) {
DMA_Handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
DMA_Handle.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
......@@ -409,11 +410,6 @@ mp_obj_t pyb_dac_write_timed(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_
DMA_Handle.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
}
DMA_Handle.Init.Mode = args[2].u_int;
DMA_Handle.Init.Priority = DMA_PRIORITY_HIGH;
DMA_Handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
DMA_Handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_HALFFULL;
DMA_Handle.Init.MemBurst = DMA_MBURST_SINGLE;
DMA_Handle.Init.PeriphBurst = DMA_PBURST_SINGLE;
HAL_DMA_Init(&DMA_Handle);
if (self->dac_channel == DAC_CHANNEL_1) {
......@@ -444,8 +440,8 @@ mp_obj_t pyb_dac_write_timed(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_
/*
// enable DMA stream
DMA_Cmd(self->dma_stream, ENABLE);
while (DMA_GetCmdStatus(self->dma_stream) == DISABLE) {
DMA_Cmd(DMA_Handle->Instance, ENABLE);
while (DMA_GetCmdStatus(DMA_Handle->Instance) == DISABLE) {
}
// enable DAC channel
......
This diff is collapsed.
......@@ -24,82 +24,58 @@
* THE SOFTWARE.
*/
// These are ordered by DMAx_Stream number, and within a stream by channel
// number. The duplicate streams are ok as long as they aren't used at the
// same time.
//
// Currently I2C and SPI are synchronous and they call dma_init/dma_deinit
// around each transfer.
// DMA1 streams
#define DMA_STREAM_I2C1_RX DMA1_Stream0
#define DMA_CHANNEL_I2C1_RX DMA_CHANNEL_1
#define DMA_STREAM_SPI3_RX DMA1_Stream2
#define DMA_CHANNEL_SPI3_RX DMA_CHANNEL_0
#define DMA_STREAM_I2C3_RX DMA1_Stream2
#define DMA_CHANNEL_I2C3_RX DMA_CHANNEL_3
#define DMA_STREAM_I2C2_RX DMA1_Stream2
#define DMA_CHANNEL_I2C2_RX DMA_CHANNEL_7
#define DMA_STREAM_SPI2_RX DMA1_Stream3
#define DMA_CHANNEL_SPI2_RX DMA_CHANNEL_0
#define DMA_STREAM_SPI2_TX DMA1_Stream4
#define DMA_CHANNEL_SPI2_TX DMA_CHANNEL_0
#define DMA_STREAM_I2C3_TX DMA1_Stream4
#define DMA_CHANNEL_I2C3_TX DMA_CHANNEL_3
#define DMA_STREAM_DAC1 DMA1_Stream5
#define DMA_CHANNEL_DAC1 DMA_CHANNEL_7
#define DMA_STREAM_DAC2 DMA1_Stream6
#define DMA_CHANNEL_DAC2 DMA_CHANNEL_7
#define DMA_STREAM_SPI3_TX DMA1_Stream7
#define DMA_CHANNEL_SPI3_TX DMA_CHANNEL_0
#define DMA_STREAM_I2C1_TX DMA1_Stream7
#define DMA_CHANNEL_I2C1_TX DMA_CHANNEL_1
#define DMA_STREAM_I2C2_TX DMA1_Stream7
#define DMA_CHANNEL_I2C2_TX DMA_CHANNEL_7
// DMA2 streams
#define DMA_STREAM_SPI1_RX DMA2_Stream2
#define DMA_CHANNEL_SPI1_RX DMA_CHANNEL_3
#define DMA_STREAM_SPI5_RX DMA2_Stream3
#define DMA_CHANNEL_SPI5_RX DMA_CHANNEL_2
#define DMA_STREAM_SDIO_RX DMA2_Stream3
#define DMA_CHANNEL_SDIO_RX DMA_CHANNEL_4
#define DMA_STREAM_SPI4_RX DMA2_Stream3
#define DMA_CHANNEL_SPI4_RX DMA_CHANNEL_5
#define DMA_STREAM_SPI5_TX DMA2_Stream4
#define DMA_CHANNEL_SPI5_TX DMA_CHANNEL_2
#define DMA_STREAM_SPI4_TX DMA2_Stream4
#define DMA_CHANNEL_SPI4_TX DMA_CHANNEL_5
#define DMA_STREAM_SPI6_TX DMA2_Stream5
#define DMA_CHANNEL_SPI6_TX DMA_CHANNEL_1
#define DMA_STREAM_SPI1_TX DMA2_Stream5
#define DMA_CHANNEL_SPI1_TX DMA_CHANNEL_3
#define DMA_STREAM_SPI6_RX DMA2_Stream6
#define DMA_CHANNEL_SPI6_RX DMA_CHANNEL_1
#define DMA_STREAM_SDIO_TX DMA2_Stream6
#define DMA_CHANNEL_SDIO_TX DMA_CHANNEL_4
#ifndef __MICROPY_INCLUDED_STMHAL_DMA_H__
#define __MICROPY_INCLUDED_STMHAL_DMA_H__
typedef struct _dma_descr_t dma_descr_t;
#if defined(MCU_SERIES_F4) || defined(MCU_SERIES_F7)
extern const dma_descr_t dma_I2C_1_RX;
extern const dma_descr_t dma_SPI_3_RX;
extern const dma_descr_t dma_I2C_3_RX;
extern const dma_descr_t dma_I2C_2_RX;
extern const dma_descr_t dma_SPI_2_RX;
extern const dma_descr_t dma_SPI_2_TX;
extern const dma_descr_t dma_I2C_3_TX;
extern const dma_descr_t dma_DAC_1_TX;
extern const dma_descr_t dma_DAC_2_TX;
extern const dma_descr_t dma_SPI_3_TX;
extern const dma_descr_t dma_I2C_1_TX;
extern const dma_descr_t dma_I2C_2_TX;
extern const dma_descr_t dma_SPI_1_RX;
extern const dma_descr_t dma_SPI_5_RX;
extern const dma_descr_t dma_SDIO_0_RX;
extern const dma_descr_t dma_SPI_4_RX;
extern const dma_descr_t dma_SPI_5_TX;
extern const dma_descr_t dma_SPI_4_TX;
extern const dma_descr_t dma_SPI_6_TX;
extern const dma_descr_t dma_SPI_1_TX;
extern const dma_descr_t dma_SPI_6_RX;
extern const dma_descr_t dma_SDIO_0_TX;
#elif defined(MCU_SERIES_L4)
extern const dma_descr_t dma_ADC_1_RX;
extern const dma_descr_t dma_ADC_2_RX;
extern const dma_descr_t dma_SPI_1_RX;
extern const dma_descr_t dma_I2C_3_TX;
extern const dma_descr_t dma_ADC_3_RX;
extern const dma_descr_t dma_SPI_1_TX;
extern const dma_descr_t dma_I2C_3_RX;
extern const dma_descr_t dma_DAC_1_TX;
extern const dma_descr_t dma_SPI_2_RX;
extern const dma_descr_t dma_I2C_2_TX;
extern const dma_descr_t dma_DAC_2_TX;
extern const dma_descr_t dma_SPI_2_TX;
extern const dma_descr_t dma_I2C_2_RX;
extern const dma_descr_t dma_I2C_1_TX;
extern const dma_descr_t dma_I2C_1_RX;
extern const dma_descr_t dma_SPI_3_RX;
extern const dma_descr_t dma_SPI_3_TX;
extern const dma_descr_t dma_SDIO_1_TX;
#endif
typedef union {
uint16_t enabled; // Used to test if both counters are == 0
......@@ -113,9 +89,11 @@ extern volatile dma_idle_count_t dma_idle;
#define DMA_IDLE_TICK_MAX (8) // 128 msec
#define DMA_IDLE_TICK(tick) (((tick) & DMA_SYSTICK_MASK) == 0)
extern const DMA_InitTypeDef dma_init_struct_spi_i2c;
void dma_init(DMA_HandleTypeDef *dma, DMA_Stream_TypeDef *dma_stream, const DMA_InitTypeDef *dma_init, uint32_t dma_channel, uint32_t direction, void *data);
void dma_deinit(DMA_HandleTypeDef *dma);
void dma_invalidate_channel(DMA_Stream_TypeDef *dma_stream, uint32_t dma_channel);
void dma_init(DMA_HandleTypeDef *dma, const dma_descr_t *dma_descr, void *data);
void dma_init_handle(DMA_HandleTypeDef *dma, const dma_descr_t *dma_descr, void *data);
void dma_deinit(const dma_descr_t *dma_descr);
void dma_invalidate_channel(const dma_descr_t *dma_descr);
void dma_idle_handler(int controller);
#endif //__MICROPY_INCLUDED_STMHAL_DMA_H__
......@@ -101,25 +101,14 @@
/// i2c.mem_read(3, 0x42, 2) # read 3 bytes from memory of slave 0x42,
/// # starting at address 2 in the slave
/// i2c.mem_write('abc', 0x42, 2, timeout=1000)
// Possible DMA configurations for I2C busses:
// I2C1_TX: DMA1_Stream6.CHANNEL_1 or DMA1_Stream7.CHANNEL_1
// I2C1_RX: DMA1_Stream0.CHANNEL_1 or DMA1_Stream5.CHANNEL_1
// I2C2_TX: DMA1_Stream7.CHANNEL_7
// I2C2_RX: DMA1_Stream2.CHANNEL_7 or DMA1_Stream3.CHANNEL_7
// I2C3_TX: DMA1_Stream4.CHANNEL_3
// I2C3_RX: DMA1_Stream2.CHANNEL_3
#define PYB_I2C_MASTER (0)
#define PYB_I2C_SLAVE (1)
typedef struct _pyb_i2c_obj_t {
mp_obj_base_t base;
I2C_HandleTypeDef *i2c;
DMA_Stream_TypeDef *tx_dma_stream;
uint32_t tx_dma_channel;
DMA_Stream_TypeDef *rx_dma_stream;
uint32_t rx_dma_channel;
const dma_descr_t *tx_dma_descr;
const dma_descr_t *rx_dma_descr;
} pyb_i2c_obj_t;
#if defined(MICROPY_HW_I2C1_SCL)
......@@ -134,24 +123,24 @@ I2C_HandleTypeDef I2CHandle3 = {.Instance = NULL};
STATIC const pyb_i2c_obj_t pyb_i2c_obj[] = {
#if defined(MICROPY_HW_I2C1_SCL)
{{&pyb_i2c_type}, &I2CHandle1, DMA_STREAM_I2C1_TX, DMA_CHANNEL_I2C1_TX, DMA_STREAM_I2C1_RX, DMA_CHANNEL_I2C1_RX},
{{&pyb_i2c_type}, &I2CHandle1, &dma_I2C_1_TX, &dma_I2C_1_RX},
#else
{{&pyb_i2c_type}, NULL, NULL, 0, NULL, 0},
{{&pyb_i2c_type}, NULL, NULL, NULL},
#endif
#if defined(MICROPY_HW_I2C2_SCL)
{{&pyb_i2c_type}, &I2CHandle2, DMA_STREAM_I2C2_TX, DMA_CHANNEL_I2C2_TX, DMA_STREAM_I2C2_RX, DMA_CHANNEL_I2C2_RX},
{{&pyb_i2c_type}, &I2CHandle2, &dma_I2C_2_TX, &dma_I2C_2_RX},
#else
{{&pyb_i2c_type}, NULL, NULL, 0, NULL, 0},
{{&pyb_i2c_type}, NULL, NULL, NULL},
#endif
#if defined(MICROPY_HW_I2C3_SCL)
{{&pyb_i2c_type}, &I2CHandle3, DMA_STREAM_I2C3_TX, DMA_CHANNEL_I2C3_TX, DMA_STREAM_I2C3_RX, DMA_CHANNEL_I2C3_RX},
{{&pyb_i2c_type}, &I2CHandle3, &dma_I2C_3_TX, &dma_I2C_3_RX},
#else
{{&pyb_i2c_type}, NULL, NULL, 0, NULL, 0},
{{&pyb_i2c_type}, NULL, NULL, NULL},
#endif
};
#if defined(MICROPY_HW_I2C_BAUDRATE_TIMING)
// The STM32F0, F3, and F7 use a TIMINGR register rather than ClockSpeed and
// The STM32F0, F3, F7 and L4 use a TIMINGR register rather than ClockSpeed and
// DutyCycle.
STATIC const struct {
......@@ -263,8 +252,8 @@ void i2c_init(I2C_HandleTypeDef *i2c) {
// invalidate the DMA channels so they are initialised on first use
const pyb_i2c_obj_t *self = &pyb_i2c_obj[i2c_unit - 1];
dma_invalidate_channel(self->tx_dma_stream, self->tx_dma_channel);
dma_invalidate_channel(self->rx_dma_stream, self->rx_dma_channel);
dma_invalidate_channel(self->tx_dma_descr);
dma_invalidate_channel(self->rx_dma_descr);
}
void i2c_deinit(I2C_HandleTypeDef *i2c) {
......@@ -528,7 +517,7 @@ STATIC mp_obj_t pyb_i2c_send(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_
// if IRQs are enabled then we can use DMA
DMA_HandleTypeDef tx_dma;
if (query_irq() == IRQ_STATE_ENABLED) {
dma_init(&tx_dma, self->tx_dma_stream, &dma_init_struct_spi_i2c, self->tx_dma_channel, DMA_MEMORY_TO_PERIPH, self->i2c);
dma_init(&tx_dma, self->tx_dma_descr, self->i2c);
self->i2c->hdmatx = &tx_dma;
self->i2c->hdmarx = NULL;
}
......@@ -538,7 +527,7 @@ STATIC mp_obj_t pyb_i2c_send(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_
if (in_master_mode(self)) {
if (args[1].u_int == PYB_I2C_MASTER_ADDRESS) {
if (query_irq() == IRQ_STATE_ENABLED) {
dma_deinit(&tx_dma);
dma_deinit(self->tx_dma_descr);
}
nlr_raise(mp_obj_new_exception_msg(&mp_type_TypeError, "addr argument required"));
}
......@@ -561,7 +550,7 @@ STATIC mp_obj_t pyb_i2c_send(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_
if (status == HAL_OK) {
status = i2c_wait_dma_finished(self->i2c, args[2].u_int);
}
dma_deinit(&tx_dma);
dma_deinit(self->tx_dma_descr);
}
if (status != HAL_OK) {
......@@ -602,7 +591,7 @@ STATIC mp_obj_t pyb_i2c_recv(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_
// if IRQs are enabled then we can use DMA
DMA_HandleTypeDef rx_dma;
if (query_irq() == IRQ_STATE_ENABLED) {
dma_init(&rx_dma, self->rx_dma_stream, &dma_init_struct_spi_i2c, self->rx_dma_channel, DMA_PERIPH_TO_MEMORY, self->i2c);
dma_init(&rx_dma, self->rx_dma_descr, self->i2c);
self->i2c->hdmatx = NULL;
self->i2c->hdmarx = &rx_dma;
}
......@@ -632,7 +621,7 @@ STATIC mp_obj_t pyb_i2c_recv(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_
if (status == HAL_OK) {
status = i2c_wait_dma_finished(self->i2c, args[2].u_int);
}
dma_deinit(&rx_dma);
dma_deinit(self->rx_dma_descr);
}
if (status != HAL_OK) {
......@@ -696,14 +685,14 @@ STATIC mp_obj_t pyb_i2c_mem_read(mp_uint_t n_args, const mp_obj_t *pos_args, mp_
status = HAL_I2C_Mem_Read(self->i2c, i2c_addr, mem_addr, mem_addr_size, (uint8_t*)vstr.buf, vstr.len, args[3].u_int);
} else {
DMA_HandleTypeDef rx_dma;
dma_init(&rx_dma, self->rx_dma_stream, &dma_init_struct_spi_i2c, self->rx_dma_channel, DMA_PERIPH_TO_MEMORY, self->i2c);
dma_init(&rx_dma, self->rx_dma_descr, self->i2c);
self->i2c->hdmatx = NULL;
self->i2c->hdmarx = &rx_dma;
status = HAL_I2C_Mem_Read_DMA(self->i2c, i2c_addr, mem_addr, mem_addr_size, (uint8_t*)vstr.buf, vstr.len);
if (status == HAL_OK) {
status = i2c_wait_dma_finished(self->i2c, args[3].u_int);
}
dma_deinit(&rx_dma);
dma_deinit(self->rx_dma_descr);
}
if (status != HAL_OK) {
......@@ -760,14 +749,14 @@ STATIC mp_obj_t pyb_i2c_mem_write(mp_uint_t n_args, const mp_obj_t *pos_args, mp
status = HAL_I2C_Mem_Write(self->i2c, i2c_addr, mem_addr, mem_addr_size, bufinfo.buf, bufinfo.len, args[3].u_int);
} else {
DMA_HandleTypeDef tx_dma;
dma_init(&tx_dma, self->tx_dma_stream, &dma_init_struct_spi_i2c, self->tx_dma_channel, DMA_MEMORY_TO_PERIPH, self->i2c);
dma_init(&tx_dma, self->tx_dma_descr, self->i2c);
self->i2c->hdmatx = &tx_dma;
self->i2c->hdmarx = NULL;
status = HAL_I2C_Mem_Write_DMA(self->i2c, i2c_addr, mem_addr, mem_addr_size, bufinfo.buf, bufinfo.len);
if (status == HAL_OK) {
status = i2c_wait_dma_finished(self->i2c, args[3].u_int);
}
dma_deinit(&tx_dma);
dma_deinit(self->tx_dma_descr);
}
if (status != HAL_OK) {
......
......@@ -63,6 +63,11 @@
#define SDIO_TRANSFER_CLK_DIV SDMMC_TRANSFER_CLK_DIV
#elif defined(MCU_SERIES_L4)
// The L4 series is not supported
#error Unsupported Processor
#endif
// TODO: Since SDIO is fundamentally half-duplex, we really only need to
......@@ -77,22 +82,6 @@
static SD_HandleTypeDef sd_handle;
static DMA_HandleTypeDef sd_rx_dma, sd_tx_dma;
// Parameters to dma_init() for SDIO tx and rx.
static const DMA_InitTypeDef dma_init_struct_sdio = {
.Channel = 0,
.Direction = 0,
.PeriphInc = DMA_PINC_DISABLE,
.MemInc = DMA_MINC_ENABLE,
.PeriphDataAlignment = DMA_PDATAALIGN_WORD,
.MemDataAlignment = DMA_MDATAALIGN_WORD,
.Mode = DMA_PFCTRL,
.Priority = DMA_PRIORITY_VERY_HIGH,
.FIFOMode = DMA_FIFOMODE_ENABLE,
.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL,
.MemBurst = DMA_MBURST_INC4,
.PeriphBurst = DMA_PBURST_INC4,
};
void sdcard_init(void) {
GPIO_InitTypeDef GPIO_Init_Structure;
......@@ -219,8 +208,7 @@ mp_uint_t sdcard_read_blocks(uint8_t *dest, uint32_t block_num, uint32_t num_blo
// we must disable USB irqs to prevent MSC contention with SD card
uint32_t basepri = raise_irq_pri(IRQ_PRI_OTG_FS);
dma_init(&sd_rx_dma, DMA_STREAM_SDIO_RX, &dma_init_struct_sdio,
DMA_CHANNEL_SDIO_RX, DMA_PERIPH_TO_MEMORY, &sd_handle);
dma_init(&sd_rx_dma, &dma_SDIO_0_RX, &sd_handle);
sd_handle.hdmarx = &sd_rx_dma;
err = HAL_SD_ReadBlocks_BlockNumber_DMA(&sd_handle, (uint32_t*)dest, block_num, SDCARD_BLOCK_SIZE, num_blocks);
......@@ -229,7 +217,7 @@ mp_uint_t sdcard_read_blocks(uint8_t *dest, uint32_t block_num, uint32_t num_blo
err = HAL_SD_CheckReadOperation(&sd_handle, 100000000);
}
dma_deinit(sd_handle.hdmarx);
dma_deinit(&dma_SDIO_0_RX);
sd_handle.hdmarx = NULL;
restore_irq_pri(basepri);
......@@ -256,9 +244,8 @@ mp_uint_t sdcard_write_blocks(const uint8_t *src, uint32_t block_num, uint32_t n
if (query_irq() == IRQ_STATE_ENABLED) {
// we must disable USB irqs to prevent MSC contention with SD card
uint32_t basepri = raise_irq_pri(IRQ_PRI_OTG_FS);
dma_init(&sd_tx_dma, DMA_STREAM_SDIO_TX, &dma_init_struct_sdio,
DMA_CHANNEL_SDIO_TX, DMA_MEMORY_TO_PERIPH, &sd_handle);
\
dma_init(&sd_rx_dma, &dma_SDIO_0_TX, &sd_handle);
sd_handle.hdmatx = &sd_tx_dma;
err = HAL_SD_WriteBlocks_BlockNumber_DMA(&sd_handle, (uint32_t*)src, block_num, SDCARD_BLOCK_SIZE, num_blocks);
......@@ -266,7 +253,7 @@ mp_uint_t sdcard_write_blocks(const uint8_t *src, uint32_t block_num, uint32_t n
// wait for DMA transfer to finish, with a large timeout
err = HAL_SD_CheckWriteOperation(&sd_handle, 100000000);
}
dma_deinit(sd_handle.hdmatx);
dma_deinit(&dma_SDIO_0_TX);
sd_handle.hdmatx = NULL;
restore_irq_pri(basepri);
......
......@@ -78,10 +78,8 @@
typedef struct _pyb_spi_obj_t {
mp_obj_base_t base;
SPI_HandleTypeDef *spi;
DMA_Stream_TypeDef *tx_dma_stream;
uint32_t tx_dma_channel;
DMA_Stream_TypeDef *rx_dma_stream;
uint32_t rx_dma_channel;
const dma_descr_t *tx_dma_descr;
const dma_descr_t *rx_dma_descr;
} pyb_spi_obj_t;
#if defined(MICROPY_HW_SPI1_SCK)
......@@ -105,34 +103,34 @@ SPI_HandleTypeDef SPIHandle6 = {.Instance = NULL};
STATIC const pyb_spi_obj_t pyb_spi_obj[] = {
#if defined(MICROPY_HW_SPI1_SCK)
{{&pyb_spi_type}, &SPIHandle1, DMA_STREAM_SPI1_TX, DMA_CHANNEL_SPI1_TX, DMA_STREAM_SPI1_RX, DMA_CHANNEL_SPI1_RX},
{{&pyb_spi_type}, &SPIHandle1, &dma_SPI_1_TX, &dma_SPI_1_RX},
#else
{{&pyb_spi_type}, NULL, NULL, 0, NULL, 0},
{{&pyb_spi_type}, NULL, NULL, NULL},
#endif
#if defined(MICROPY_HW_SPI2_SCK)
{{&pyb_spi_type}, &SPIHandle2, DMA_STREAM_SPI2_TX, DMA_CHANNEL_SPI2_TX, DMA_STREAM_SPI2_RX, DMA_CHANNEL_SPI2_RX},
{{&pyb_spi_type}, &SPIHandle2, &dma_SPI_2_TX, &dma_SPI_2_RX},
#else
{{&pyb_spi_type}, NULL, NULL, 0, NULL, 0},
{{&pyb_spi_type}, NULL, NULL, NULL},
#endif
#if defined(MICROPY_HW_SPI3_SCK)
{{&pyb_spi_type}, &SPIHandle3, DMA_STREAM_SPI3_TX, DMA_CHANNEL_SPI3_TX, DMA_STREAM_SPI3_RX, DMA_CHANNEL_SPI3_RX},
{{&pyb_spi_type}, &SPIHandle3, &dma_SPI_3_TX, &dma_SPI_3_RX},
#else
{{&pyb_spi_type}, NULL, NULL, 0, NULL, 0},
{{&pyb_spi_type}, NULL, NULL, NULL},
#endif
#if defined(MICROPY_HW_SPI4_SCK)
{{&pyb_spi_type}, &SPIHandle4, DMA_STREAM_SPI4_TX, DMA_CHANNEL_SPI4_TX, DMA_STREAM_SPI4_RX, DMA_CHANNEL_SPI4_RX},
{{&pyb_spi_type}, &SPIHandle4, &dma_SPI_4_TX, &dma_SPI_4_RX},
#else
{{&pyb_spi_type}, NULL, NULL, 0, NULL, 0},
{{&pyb_spi_type}, NULL, NULL, NULL},
#endif
#if defined(MICROPY_HW_SPI5_SCK)
{{&pyb_spi_type}, &SPIHandle5, DMA_STREAM_SPI5_TX, DMA_CHANNEL_SPI5_TX, DMA_STREAM_SPI5_RX, DMA_CHANNEL_SPI5_RX},
{{&pyb_spi_type}, &SPIHandle5, &dma_SPI_5_TX, &dma_SPI_5_RX},
#else
{{&pyb_spi_type}, NULL, NULL, 0, NULL, 0},
{{&pyb_spi_type}, NULL, NULL, NULL},
#endif
#if defined(MICROPY_HW_SPI6_SCK)
{{&pyb_spi_type}, &SPIHandle6, DMA_STREAM_SPI6_TX, DMA_CHANNEL_SPI6_TX, DMA_STREAM_SPI6_RX, DMA_CHANNEL_SPI6_RX},
{{&pyb_spi_type}, &SPIHandle6, &dma_SPI_6_TX, &dma_SPI_6_RX},
#else
{{&pyb_spi_type}, NULL, NULL, 0, NULL, 0},
{{&pyb_spi_type}, NULL, NULL, NULL},
#endif
};
......@@ -257,8 +255,8 @@ void spi_init(SPI_HandleTypeDef *spi, bool enable_nss_pin) {
// After calling HAL_SPI_Init() it seems that the DMA gets disconnected if
// it was previously configured. So we invalidate the DMA channel to force
// an initialisation the next time we use it.
dma_invalidate_channel(self->tx_dma_stream, self->tx_dma_channel);
dma_invalidate_channel(self->rx_dma_stream, self->rx_dma_channel);
dma_invalidate_channel(self->tx_dma_descr);
dma_invalidate_channel(self->rx_dma_descr);
}
void spi_deinit(SPI_HandleTypeDef *spi) {
......@@ -553,14 +551,14 @@ STATIC mp_obj_t pyb_spi_send(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_
status = HAL_SPI_Transmit(self->spi, bufinfo.buf, bufinfo.len, args[1].u_int);
} else {
DMA_HandleTypeDef tx_dma;
dma_init(&tx_dma, self->tx_dma_stream, &dma_init_struct_spi_i2c, self->tx_dma_channel, DMA_MEMORY_TO_PERIPH, self->spi);
dma_init(&tx_dma, self->tx_dma_descr, self->spi);
self->spi->hdmatx = &tx_dma;
self->spi->hdmarx = NULL;
status = HAL_SPI_Transmit_DMA(self->spi, bufinfo.buf, bufinfo.len);
if (status == HAL_OK) {
status = spi_wait_dma_finished(self->spi, args[1].u_int);
}
dma_deinit(&tx_dma);
dma_deinit(self->tx_dma_descr);
}
if (status != HAL_OK) {
......@@ -606,12 +604,12 @@ STATIC mp_obj_t pyb_spi_recv(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_
DMA_HandleTypeDef tx_dma, rx_dma;
if (self->spi->Init.Mode == SPI_MODE_MASTER) {
// in master mode the HAL actually does a TransmitReceive call
dma_init(&tx_dma, self->tx_dma_stream, &dma_init_struct_spi_i2c, self->tx_dma_channel, DMA_MEMORY_TO_PERIPH, self->spi);
dma_init(&tx_dma, self->tx_dma_descr, self->spi);
self->spi->hdmatx = &tx_dma;
} else {
self->spi->hdmatx = NULL;
}
dma_init(&rx_dma, self->rx_dma_stream, &dma_init_struct_spi_i2c, self->rx_dma_channel, DMA_PERIPH_TO_MEMORY, self->spi);
dma_init(&rx_dma, self->rx_dma_descr, self->spi);
self->spi->hdmarx = &rx_dma;
status = HAL_SPI_Receive_DMA(self->spi, (uint8_t*)vstr.buf, vstr.len);
......@@ -619,9 +617,9 @@ STATIC mp_obj_t pyb_spi_recv(mp_uint_t n_args, const mp_obj_t *pos_args, mp_map_
status = spi_wait_dma_finished(self->spi, args[1].u_int);
}
if (self->spi->hdmatx != NULL) {
dma_deinit(&tx_dma);
dma_deinit(self->tx_dma_descr);
}
dma_deinit(&rx_dma);
dma_deinit(self->rx_dma_descr);
}
if (status != HAL_OK) {
......@@ -701,16 +699,16 @@ STATIC mp_obj_t pyb_spi_send_recv(mp_uint_t n_args, const mp_obj_t *pos_args, mp
status = HAL_SPI_TransmitReceive(self->spi, bufinfo_send.buf, bufinfo_recv.buf, bufinfo_send.len, args[2].u_int);
} else {
DMA_HandleTypeDef tx_dma, rx_dma;
dma_init(&tx_dma, self->tx_dma_stream, &dma_init_struct_spi_i2c, self->tx_dma_channel, DMA_MEMORY_TO_PERIPH, self->spi);
dma_init(&tx_dma, self->tx_dma_descr, self->spi);
self->spi->hdmatx = &tx_dma;
dma_init(&rx_dma, self->rx_dma_stream, &dma_init_struct_spi_i2c, self->rx_dma_channel, DMA_PERIPH_TO_MEMORY, self->spi);
dma_init(&rx_dma, self->rx_dma_descr, self->spi);
self->spi->hdmarx = &rx_dma;
status = HAL_SPI_TransmitReceive_DMA(self->spi, bufinfo_send.buf, bufinfo_recv.buf, bufinfo_send.len);
if (status == HAL_OK) {
status = spi_wait_dma_finished(self->spi, args[2].u_int);
}
dma_deinit(&tx_dma);
dma_deinit(&rx_dma);
dma_deinit(self->tx_dma_descr);
dma_deinit(self->rx_dma_descr);
}
if (status != HAL_OK) {
......
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