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uPython-mirror
Commits
c6f1d47d
Commit
c6f1d47d
authored
Aug 15, 2015
by
Dave Hylands
Browse files
stmhal: Enable I & D caches for M7
parent
3179d23c
Changes
1
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Side-by-side
stmhal/system_stm32.c
View file @
c6f1d47d
...
...
@@ -316,3 +316,13 @@ void SystemClock_Config(void)
RCC
->
DCKCFGR2
=
0
;
#endif
}
void
HAL_MspInit
(
void
)
{
#if defined(MCU_SERIES_F7)
/* Enable I-Cache */
SCB_EnableICache
();
/* Enable D-Cache */
SCB_EnableDCache
();
#endif
}
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