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TASTE
uPython-mirror
Commits
b2ebb161
Commit
b2ebb161
authored
Jan 19, 2014
by
Damien George
Browse files
stm: Upgrade ST peripheral library from 1.1.0 to 1.3.0.
parent
12777538
Changes
41
Expand all
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stm/Makefile
View file @
b2ebb161
...
...
@@ -22,7 +22,7 @@ LD = arm-none-eabi-ld
OBJCOPY
=
arm-none-eabi-objcopy
SIZE
=
arm-none-eabi-size
CFLAGS_CORTEX_M4
=
-mthumb
-mtune
=
cortex-m4
-mabi
=
aapcs-linux
-mcpu
=
cortex-m4
-mfpu
=
fpv4-sp-d16
-mfloat-abi
=
hard
-fsingle-precision-constant
-Wdouble-promotion
-DSTM32F40
XX
-DHSE_VALUE
=
8000000
CFLAGS_CORTEX_M4
=
-mthumb
-mtune
=
cortex-m4
-mabi
=
aapcs-linux
-mcpu
=
cortex-m4
-mfpu
=
fpv4-sp-d16
-mfloat-abi
=
hard
-fsingle-precision-constant
-Wdouble-promotion
-DSTM32F40
_41xxx
-DUSE_STDPERIPH_DRIVER
-DHSE_VALUE
=
8000000
CFLAGS
=
-I
.
-I
$(PY_SRC)
-I
$(FATFSSRC)
-I
$(CMSIS)
-I
$(STMSRC)
-Wall
-ansi
-std
=
gnu99
$(CFLAGS_CORTEX_M4)
-D
$(TARGET)
#CFLAGS += -I$(STMOTGSRC) -DUSE_HOST_MODE -DUSE_OTG_MODE
...
...
@@ -85,6 +85,7 @@ SRC_STM = \
stm32f4xx_spi.c
\
stm32f4xx_dac.c
\
stm32f4xx_rng.c
\
stm32f4xx_i2c.c
\
usb_core.c
\
usb_dcd.c
\
usb_dcd_int.c
\
...
...
stm/adc.c
View file @
b2ebb161
#include
<stdio.h>
#include
<stm32f4xx_rcc.h>
#include
<stm32f4xx_gpio.h>
#include
<stm32f4xx_adc.h>
#include
<stm32f4xx.h>
#include
"misc.h"
#include
"mpconfig.h"
...
...
@@ -14,7 +12,7 @@
#define ADC_NUM_CHANNELS (16)
/* Internally connected ADC channels Temp/VBAT/VREF*/
#if defined (STM32F40XX) || defined(STM32F41XX)
#if defined (STM32F40XX) || defined(STM32F41XX)
|| defined(STM32F40_41xxx)
#define ADC_TEMP_CHANNEL (16)
#define ADC_VBAT_CHANNEL (18)
#define ADC_VREF_CHANNEL (17)
...
...
@@ -29,7 +27,7 @@
#define CORE_TEMP_AVG_SLOPE (3)
/* (2.5mv/3.3v)*(2^ADC resoultion) */
/* VBAT divider */
#if defined (STM32F40XX) || defined(STM32F41XX)
#if defined (STM32F40XX) || defined(STM32F41XX)
|| defined(STM32F40_41xxx)
#define VBAT_DIV (2)
#elif defined (STM32F42XX) || defined(STM32F43XX)
#define VBAT_DIV (4)
...
...
stm/i2c.c
View file @
b2ebb161
#include
<stdio.h>
#include
<stm32f4xx.h>
#include
<stm32f4xx_rcc.h>
#include
<stm32f4xx_gpio.h>
#include
"misc.h"
#include
"systick.h"
...
...
stm/lib/stm32f4xx.h
View file @
b2ebb161
This diff is collapsed.
Click to expand it.
stm/lib/stm32f4xx_adc.c
View file @
b2ebb161
...
...
@@ -105,7 +105,6 @@
/* Includes ------------------------------------------------------------------*/
#include
"stm32f4xx_adc.h"
#include
"stm32f4xx_rcc.h"
#include
"stm32f4xx_conf.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
...
...
stm/lib/stm32f4xx_conf.h
View file @
b2ebb161
...
...
@@ -2,8 +2,8 @@
******************************************************************************
* @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_conf.h
* @author MCD Application Team
* @version V1.
1
.0
* @date 1
8-January
-2013
* @version V1.
3
.0
* @date 1
3-November
-2013
* @brief Library configuration file.
******************************************************************************
* @attention
...
...
@@ -31,32 +31,60 @@
/* Includes ------------------------------------------------------------------*/
/* Uncomment the line below to enable peripheral header file inclusion */
//#include "stm32f4xx_adc.h"
//#include "stm32f4xx_can.h"
#include
"stm32f4xx_adc.h"
//#include "stm32f4xx_crc.h"
//#include "stm32f4xx_cryp.h"
//#include "stm32f4xx_dac.h"
//#include "stm32f4xx_dbgmcu.h"
//#include "stm32f4xx_dcmi.h"
//#include "stm32f4xx_dma.h"
//#include "stm32f4xx_exti.h"
//#include "stm32f4xx_flash.h"
//#include "stm32f4xx_fsmc.h"
//#include "stm32f4xx_hash.h"
//#include "stm32f4xx_gpio.h"
//#include "stm32f4xx_i2c.h"
#include
"stm32f4xx_dma.h"
#include
"stm32f4xx_exti.h"
#include
"stm32f4xx_flash.h"
#include
"stm32f4xx_gpio.h"
#include
"stm32f4xx_i2c.h"
//#include "stm32f4xx_iwdg.h"
//#include "stm32f4xx_pwr.h"
//#include "stm32f4xx_rcc.h"
//#include "stm32f4xx_rng.h"
//#include "stm32f4xx_rtc.h"
//#include "stm32f4xx_sdio.h"
//#include "stm32f4xx_spi.h"
//#include "stm32f4xx_syscfg.h"
//#include "stm32f4xx_tim.h"
//#include "stm32f4xx_usart.h"
#include
"stm32f4xx_pwr.h"
#include
"stm32f4xx_rcc.h"
#include
"stm32f4xx_rtc.h"
#include
"stm32f4xx_sdio.h"
#include
"stm32f4xx_spi.h"
#include
"stm32f4xx_syscfg.h"
#include
"stm32f4xx_tim.h"
#include
"stm32f4xx_usart.h"
//#include "stm32f4xx_wwdg.h"
//#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
#include
"stm_misc.h"
/* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
#if defined (STM32F429_439xx)
#include
"stm32f4xx_cryp.h"
#include
"stm32f4xx_hash.h"
#include
"stm32f4xx_rng.h"
#include
"stm32f4xx_can.h"
#include
"stm32f4xx_dac.h"
#include
"stm32f4xx_dcmi.h"
#include
"stm32f4xx_dma2d.h"
#include
"stm32f4xx_fmc.h"
#include
"stm32f4xx_ltdc.h"
#include
"stm32f4xx_sai.h"
#endif
/* STM32F429_439xx */
#if defined (STM32F427_437xx)
#include
"stm32f4xx_cryp.h"
#include
"stm32f4xx_hash.h"
#include
"stm32f4xx_rng.h"
#include
"stm32f4xx_can.h"
#include
"stm32f4xx_dac.h"
#include
"stm32f4xx_dcmi.h"
#include
"stm32f4xx_dma2d.h"
#include
"stm32f4xx_fmc.h"
#include
"stm32f4xx_sai.h"
#endif
/* STM32F427_437xx */
#if defined (STM32F40_41xxx)
//#include "stm32f4xx_cryp.h"
//#include "stm32f4xx_hash.h"
#include
"stm32f4xx_rng.h"
//#include "stm32f4xx_can.h"
#include
"stm32f4xx_dac.h"
//#include "stm32f4xx_dcmi.h"
//#include "stm32f4xx_fsmc.h"
#endif
/* STM32F40_41xxx */
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
...
...
stm/lib/stm32f4xx_dac.c
View file @
b2ebb161
...
...
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dac.c
* @author MCD Application Team
* @version V1.
1
.0
* @date
11-January
-2013
* @version V1.
3
.0
* @date
08-November
-2013
* @brief This file provides firmware functions to manage the following
* functionalities of the Digital-to-Analog Converter (DAC) peripheral:
* + DAC channels configuration: trigger, output buffer, data format
...
...
@@ -128,7 +128,6 @@
/* Includes ------------------------------------------------------------------*/
#include
"stm32f4xx_conf.h"
#include
"stm32f4xx_dac.h"
#include
"stm32f4xx_rcc.h"
...
...
stm/lib/stm32f4xx_dac.h
View file @
b2ebb161
...
...
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dac.h
* @author MCD Application Team
* @version V1.
1
.0
* @date
11-January
-2013
* @version V1.
3
.0
* @date
08-November
-2013
* @brief This file contains all the functions prototypes for the DAC firmware
* library.
******************************************************************************
...
...
stm/lib/stm32f4xx_dma.c
View file @
b2ebb161
...
...
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dma.c
* @author MCD Application Team
* @version V1.
1
.0
* @date
11-January
-2013
* @version V1.
3
.0
* @date
08-November
-2013
* @brief This file provides firmware functions to manage the following
* functionalities of the Direct Memory Access controller (DMA):
* + Initialization and Configuration
...
...
@@ -121,7 +121,6 @@
*/
/* Includes ------------------------------------------------------------------*/
#include
"stm32f4xx_conf.h"
#include
"stm32f4xx_dma.h"
#include
"stm32f4xx_rcc.h"
...
...
stm/lib/stm32f4xx_dma.h
View file @
b2ebb161
...
...
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dma.h
* @author MCD Application Team
* @version V1.
1
.0
* @date
11-January
-2013
* @version V1.
3
.0
* @date
08-November
-2013
* @brief This file contains all the functions prototypes for the DMA firmware
* library.
******************************************************************************
...
...
stm/lib/stm32f4xx_exti.c
View file @
b2ebb161
...
...
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_exti.c
* @author MCD Application Team
* @version V1.
1
.0
* @date
11-January
-2013
* @version V1.
3
.0
* @date
08-November
-2013
* @brief This file provides firmware functions to manage the following
* functionalities of the EXTI peripheral:
* + Initialization and Configuration
...
...
@@ -65,7 +65,6 @@
*/
/* Includes ------------------------------------------------------------------*/
#include
"stm32f4xx_conf.h"
#include
"stm32f4xx_exti.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
...
...
@@ -264,13 +263,11 @@ void EXTI_ClearFlag(uint32_t EXTI_Line)
*/
ITStatus
EXTI_GetITStatus
(
uint32_t
EXTI_Line
)
{
ITStatus
bitstatus
=
RESET
;
uint32_t
enablestatus
=
0
;
FlagStatus
bitstatus
=
RESET
;
/* Check the parameters */
assert_param
(
IS_GET_EXTI_LINE
(
EXTI_Line
));
enablestatus
=
EXTI
->
IMR
&
EXTI_Line
;
if
(((
EXTI
->
PR
&
EXTI_Line
)
!=
(
uint32_t
)
RESET
)
&&
(
enablestatus
!=
(
uint32_t
)
RESET
))
if
((
EXTI
->
PR
&
EXTI_Line
)
!=
(
uint32_t
)
RESET
)
{
bitstatus
=
SET
;
}
...
...
@@ -279,6 +276,7 @@ ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
bitstatus
=
RESET
;
}
return
bitstatus
;
}
/**
...
...
stm/lib/stm32f4xx_exti.h
View file @
b2ebb161
...
...
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_exti.h
* @author MCD Application Team
* @version V1.
1
.0
* @date
11-January
-2013
* @version V1.
3
.0
* @date
08-November
-2013
* @brief This file contains all the functions prototypes for the EXTI firmware
* library.
******************************************************************************
...
...
stm/lib/stm32f4xx_flash.c
View file @
b2ebb161
This diff is collapsed.
Click to expand it.
stm/lib/stm32f4xx_flash.h
View file @
b2ebb161
...
...
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_flash.h
* @author MCD Application Team
* @version V1.
1
.0
* @date
11-January
-2013
* @version V1.
3
.0
* @date
08-November
-2013
* @brief This file contains all the functions prototypes for the FLASH
* firmware library.
******************************************************************************
...
...
@@ -52,6 +52,7 @@
typedef
enum
{
FLASH_BUSY
=
1
,
FLASH_ERROR_RD
,
FLASH_ERROR_PGS
,
FLASH_ERROR_PGP
,
FLASH_ERROR_PGA
,
...
...
@@ -78,6 +79,15 @@ typedef enum
#define FLASH_Latency_5 ((uint8_t)0x0005)
/*!< FLASH Five Latency cycles */
#define FLASH_Latency_6 ((uint8_t)0x0006)
/*!< FLASH Six Latency cycles */
#define FLASH_Latency_7 ((uint8_t)0x0007)
/*!< FLASH Seven Latency cycles */
#define FLASH_Latency_8 ((uint8_t)0x0008)
/*!< FLASH Eight Latency cycles */
#define FLASH_Latency_9 ((uint8_t)0x0009)
/*!< FLASH Nine Latency cycles */
#define FLASH_Latency_10 ((uint8_t)0x000A)
/*!< FLASH Ten Latency cycles */
#define FLASH_Latency_11 ((uint8_t)0x000B)
/*!< FLASH Eleven Latency cycles */
#define FLASH_Latency_12 ((uint8_t)0x000C)
/*!< FLASH Twelve Latency cycles */
#define FLASH_Latency_13 ((uint8_t)0x000D)
/*!< FLASH Thirteen Latency cycles */
#define FLASH_Latency_14 ((uint8_t)0x000E)
/*!< FLASH Fourteen Latency cycles */
#define FLASH_Latency_15 ((uint8_t)0x000F)
/*!< FLASH Fifteen Latency cycles */
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
((
LATENCY
)
==
FLASH_Latency_1
)
||
\
...
...
@@ -86,8 +96,15 @@ typedef enum
((
LATENCY
)
==
FLASH_Latency_4
)
||
\
((
LATENCY
)
==
FLASH_Latency_5
)
||
\
((
LATENCY
)
==
FLASH_Latency_6
)
||
\
((
LATENCY
)
==
FLASH_Latency_7
))
((
LATENCY
)
==
FLASH_Latency_7
)
||
\
((
LATENCY
)
==
FLASH_Latency_8
)
||
\
((
LATENCY
)
==
FLASH_Latency_9
)
||
\
((
LATENCY
)
==
FLASH_Latency_10
)
||
\
((
LATENCY
)
==
FLASH_Latency_11
)
||
\
((
LATENCY
)
==
FLASH_Latency_12
)
||
\
((
LATENCY
)
==
FLASH_Latency_13
)
||
\
((
LATENCY
)
==
FLASH_Latency_14
)
||
\
((
LATENCY
)
==
FLASH_Latency_15
))
/**
* @}
*/
...
...
@@ -149,8 +166,20 @@ typedef enum
((
SECTOR
)
==
FLASH_Sector_20
)
||
((
SECTOR
)
==
FLASH_Sector_21
)
||
\
((
SECTOR
)
==
FLASH_Sector_22
)
||
((
SECTOR
)
==
FLASH_Sector_23
))
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x081FFFFF)) ||\
(((
ADDRESS
)
>=
0x1FFF7800
)
&&
((
ADDRESS
)
<
0x1FFF7A0F
)))
#endif
/* STM32F427_437xx || STM32F429_439xx */
#if defined (STM32F40_41xxx)
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\
(((
ADDRESS
)
>=
0x1FFF7800
)
&&
((
ADDRESS
)
<
0x1FFF7A0F
)))
#endif
/* STM32F40_41xxx */
#if defined (STM32F401xx)
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) < 0x0803FFFF)) ||\
(((
ADDRESS
)
>=
0x1FFF7800
)
&&
((
ADDRESS
)
<
0x1FFF7A0F
)))
#endif
/* STM32F401xx */
/**
* @}
*/
...
...
@@ -189,6 +218,50 @@ typedef enum
* @}
*/
/** @defgroup Selection_Protection_Mode
* @{
*/
#define OB_PcROP_Disable ((uint8_t)0x00)
/*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
#define OB_PcROP_Enable ((uint8_t)0x80)
/*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */
#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PcROP_Disable) || ((PCROP) == OB_PcROP_Enable))
/**
* @}
*/
/** @defgroup Option_Bytes_PC_ReadWrite_Protection
* @{
*/
#define OB_PCROP_Sector_0 ((uint32_t)0x00000001)
/*!< PC Read/Write protection of Sector0 */
#define OB_PCROP_Sector_1 ((uint32_t)0x00000002)
/*!< PC Read/Write protection of Sector1 */
#define OB_PCROP_Sector_2 ((uint32_t)0x00000004)
/*!< PC Read/Write protection of Sector2 */
#define OB_PCROP_Sector_3 ((uint32_t)0x00000008)
/*!< PC Read/Write protection of Sector3 */
#define OB_PCROP_Sector_4 ((uint32_t)0x00000010)
/*!< PC Read/Write protection of Sector4 */
#define OB_PCROP_Sector_5 ((uint32_t)0x00000020)
/*!< PC Read/Write protection of Sector5 */
#define OB_PCROP_Sector_6 ((uint32_t)0x00000040)
/*!< PC Read/Write protection of Sector6 */
#define OB_PCROP_Sector_7 ((uint32_t)0x00000080)
/*!< PC Read/Write protection of Sector7 */
#define OB_PCROP_Sector_8 ((uint32_t)0x00000100)
/*!< PC Read/Write protection of Sector8 */
#define OB_PCROP_Sector_9 ((uint32_t)0x00000200)
/*!< PC Read/Write protection of Sector9 */
#define OB_PCROP_Sector_10 ((uint32_t)0x00000400)
/*!< PC Read/Write protection of Sector10 */
#define OB_PCROP_Sector_11 ((uint32_t)0x00000800)
/*!< PC Read/Write protection of Sector11 */
#define OB_PCROP_Sector_12 ((uint32_t)0x00000001)
/*!< PC Read/Write protection of Sector12 */
#define OB_PCROP_Sector_13 ((uint32_t)0x00000002)
/*!< PC Read/Write protection of Sector13 */
#define OB_PCROP_Sector_14 ((uint32_t)0x00000004)
/*!< PC Read/Write protection of Sector14 */
#define OB_PCROP_Sector_15 ((uint32_t)0x00000008)
/*!< PC Read/Write protection of Sector15 */
#define OB_PCROP_Sector_16 ((uint32_t)0x00000010)
/*!< PC Read/Write protection of Sector16 */
#define OB_PCROP_Sector_17 ((uint32_t)0x00000020)
/*!< PC Read/Write protection of Sector17 */
#define OB_PCROP_Sector_18 ((uint32_t)0x00000040)
/*!< PC Read/Write protection of Sector18 */
#define OB_PCROP_Sector_19 ((uint32_t)0x00000080)
/*!< PC Read/Write protection of Sector19 */
#define OB_PCROP_Sector_20 ((uint32_t)0x00000100)
/*!< PC Read/Write protection of Sector20 */
#define OB_PCROP_Sector_21 ((uint32_t)0x00000200)
/*!< PC Read/Write protection of Sector21 */
#define OB_PCROP_Sector_22 ((uint32_t)0x00000400)
/*!< PC Read/Write protection of Sector22 */
#define OB_PCROP_Sector_23 ((uint32_t)0x00000800)
/*!< PC Read/Write protection of Sector23 */
#define OB_PCROP_Sector_All ((uint32_t)0x00000FFF)
/*!< PC Read/Write protection of all Sectors */
#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
/**
* @}
*/
/** @defgroup FLASH_Option_Bytes_Read_Protection
* @{
*/
...
...
@@ -246,6 +319,16 @@ typedef enum
/**
* @}
*/
/** @defgroup FLASH_Dual_Boot
* @{
*/
#define OB_Dual_BootEnabled ((uint8_t)0x10)
/*!< Dual Bank Boot Enable */
#define OB_Dual_BootDisabled ((uint8_t)0x00)
/*!< Dual Bank Boot Disable, always boot on User Flash */
#define IS_OB_BOOT(BOOT) (((BOOT) == OB_Dual_BootEnabled) || ((BOOT) == OB_Dual_BootDisabled))
/**
* @}
*/
/** @defgroup FLASH_Interrupts
* @{
...
...
@@ -266,12 +349,13 @@ typedef enum
#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020)
/*!< FLASH Programming Alignment error flag */
#define FLASH_FLAG_PGPERR ((uint32_t)0x00000040)
/*!< FLASH Programming Parallelism error flag */
#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080)
/*!< FLASH Programming Sequence error flag */
#define FLASH_FLAG_RDERR ((uint32_t)0x00000100)
/*!< Read Protection error flag (PCROP) */
#define FLASH_FLAG_BSY ((uint32_t)0x00010000)
/*!< FLASH Busy flag */
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFE0C) == 0x00000000) && ((FLAG) != 0x00000000))
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \
((
FLAG
)
==
FLASH_FLAG_WRPERR
)
||
((
FLAG
)
==
FLASH_FLAG_PGAERR
)
||
\
((
FLAG
)
==
FLASH_FLAG_PGPERR
)
||
((
FLAG
)
==
FLASH_FLAG_PGSERR
)
||
\
((
FLAG
)
==
FLASH_FLAG_BSY
))
((
FLAG
)
==
FLASH_FLAG_BSY
)
||
((
FLAG
)
==
FLASH_FLAG_RDERR
)
)
/**
* @}
*/
...
...
@@ -346,23 +430,31 @@ void FLASH_Unlock(void);
void
FLASH_Lock
(
void
);
FLASH_Status
FLASH_EraseSector
(
uint32_t
FLASH_Sector
,
uint8_t
VoltageRange
);
FLASH_Status
FLASH_EraseAllSectors
(
uint8_t
VoltageRange
);
FLASH_Status
FLASH_EraseAllBank1Sectors
(
uint8_t
VoltageRange
);
FLASH_Status
FLASH_EraseAllBank2Sectors
(
uint8_t
VoltageRange
);
FLASH_Status
FLASH_ProgramDoubleWord
(
uint32_t
Address
,
uint64_t
Data
);
FLASH_Status
FLASH_ProgramWord
(
uint32_t
Address
,
uint32_t
Data
);
FLASH_Status
FLASH_ProgramHalfWord
(
uint32_t
Address
,
uint16_t
Data
);
FLASH_Status
FLASH_ProgramByte
(
uint32_t
Address
,
uint8_t
Data
);
/* Option Bytes Programming functions *****************************************/
void
FLASH_OB_Unlock
(
void
);
void
FLASH_OB_Unlock
(
void
);
void
FLASH_OB_Lock
(
void
);
void
FLASH_OB_WRPConfig
(
uint32_t
OB_WRP
,
FunctionalState
NewState
);
void
FLASH_OB_WRP1Config
(
uint32_t
OB_WRP
,
FunctionalState
NewState
);
void
FLASH_OB_PCROPSelectionConfig
(
uint8_t
OB_PcROP
);
void
FLASH_OB_PCROPConfig
(
uint32_t
OB_PCROP
,
FunctionalState
NewState
);
void
FLASH_OB_PCROP1Config
(
uint32_t
OB_PCROP
,
FunctionalState
NewState
);
void
FLASH_OB_RDPConfig
(
uint8_t
OB_RDP
);
void
FLASH_OB_UserConfig
(
uint8_t
OB_IWDG
,
uint8_t
OB_STOP
,
uint8_t
OB_STDBY
);
void
FLASH_OB_BORConfig
(
uint8_t
OB_BOR
);
void
FLASH_OB_BootConfig
(
uint8_t
OB_BOOT
);
FLASH_Status
FLASH_OB_Launch
(
void
);
uint8_t
FLASH_OB_GetUser
(
void
);
uint16_t
FLASH_OB_GetWRP
(
void
);
uint16_t
FLASH_OB_GetWRP1
(
void
);
uint16_t
FLASH_OB_GetPCROP
(
void
);
uint16_t
FLASH_OB_GetPCROP1
(
void
);
FlagStatus
FLASH_OB_GetRDP
(
void
);
uint8_t
FLASH_OB_GetBOR
(
void
);
...
...
stm/lib/stm32f4xx_gpio.c
View file @
b2ebb161
...
...
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_gpio.c
* @author MCD Application Team
* @version V1.
1
.0
* @date
11-January
-2013
* @version V1.
3
.0
* @date
08-November
-2013
* @brief This file provides firmware functions to manage the following
* functionalities of the GPIO peripheral:
* + Initialization and Configuration
...
...
@@ -81,7 +81,6 @@
*/
/* Includes ------------------------------------------------------------------*/
#include
"stm32f4xx_conf.h"
#include
"stm32f4xx_gpio.h"
#include
"stm32f4xx_rcc.h"
...
...
@@ -120,8 +119,9 @@
/**
* @brief De-initializes the GPIOx peripheral registers to their default reset values.
* @note By default, The GPIO pins are configured in input floating mode (except JTAG pins).
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @retval None
*/
void
GPIO_DeInit
(
GPIO_TypeDef
*
GPIOx
)
...
...
@@ -169,20 +169,32 @@ void GPIO_DeInit(GPIO_TypeDef* GPIOx)
RCC_AHB1PeriphResetCmd
(
RCC_AHB1Periph_GPIOH
,
ENABLE
);
RCC_AHB1PeriphResetCmd
(
RCC_AHB1Periph_GPIOH
,
DISABLE
);
}
else
if
(
GPIOx
==
GPIOI
)
{
RCC_AHB1PeriphResetCmd
(
RCC_AHB1Periph_GPIOI
,
ENABLE
);
RCC_AHB1PeriphResetCmd
(
RCC_AHB1Periph_GPIOI
,
DISABLE
);
}
else
if
(
GPIOx
==
GPIOJ
)
{
RCC_AHB1PeriphResetCmd
(
RCC_AHB1Periph_GPIOJ
,
ENABLE
);
RCC_AHB1PeriphResetCmd
(
RCC_AHB1Periph_GPIOJ
,
DISABLE
);
}
else
{
if
(
GPIOx
==
GPIO
I
)
if
(
GPIOx
==
GPIO
K
)
{
RCC_AHB1PeriphResetCmd
(
RCC_AHB1Periph_GPIO
I
,
ENABLE
);
RCC_AHB1PeriphResetCmd
(
RCC_AHB1Periph_GPIO
I
,
DISABLE
);
RCC_AHB1PeriphResetCmd
(
RCC_AHB1Periph_GPIO
K
,
ENABLE
);
RCC_AHB1PeriphResetCmd
(
RCC_AHB1Periph_GPIO
K
,
DISABLE
);
}
}
}
/**
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
...
...
@@ -255,8 +267,9 @@ void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
* @note The configuration of the locked GPIO pins can no longer be modified
* until the next reset.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_Pin: specifies the port bit to be locked.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
...
...
@@ -300,8 +313,9 @@ void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
/**
* @brief Reads the specified input port pin.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
* @retval The input port pin value.
...
...
@@ -327,8 +341,9 @@ uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
/**
* @brief Reads the specified GPIO input data port.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @retval GPIO input data port value.
*/
uint16_t
GPIO_ReadInputData
(
GPIO_TypeDef
*
GPIOx
)
...
...
@@ -341,8 +356,9 @@ uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
/**
* @brief Reads the specified output data port bit.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
* @retval The output port pin value.
...
...
@@ -368,8 +384,9 @@ uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
/**
* @brief Reads the specified GPIO output data port.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @retval GPIO output data port value.
*/
uint16_t
GPIO_ReadOutputData
(
GPIO_TypeDef
*
GPIOx
)
...
...
@@ -385,8 +402,9 @@ uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
* @note This functions uses GPIOx_BSRR register to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_Pin: specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
...
...
@@ -405,8 +423,9 @@ void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
* @note This functions uses GPIOx_BSRR register to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_Pin: specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
* @retval None
...
...
@@ -422,8 +441,9 @@ void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
/**
* @brief Sets or clears the selected data port bit.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
* @param BitVal: specifies the value to be written to the selected bit.
...
...
@@ -451,8 +471,9 @@ void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
/**
* @brief Writes data to the specified GPIO data port.
* @param GPIOx: where x can be (A..I) to select the GPIO peripheral for
* STM32F40xx/41xx and STM32F427x/437x devices.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices
* x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices.
* x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices.
* @param PortVal: specifies the value to be written to the port output data register.
* @retval None
*/
...
...
@@ -466,8 +487,9 @@ void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)