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uPython-mirror
Commits
8517bce6
Commit
8517bce6
authored
Jan 21, 2014
by
Damien George
Browse files
Merge pull request #202 from iabdalkader/master
Remove hardcoded PLL_M value
parents
d30e0194
4578ced2
Changes
2
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stm/Makefile
View file @
8517bce6
...
...
@@ -18,6 +18,7 @@ FATFSSRC=fatfs
CC3KSRC
=
cc3k
DFU
=
../tools/dfu.py
TARGET
=
PYBOARD
OSC_VALUE
=
8000000
AS
=
arm-none-eabi-as
CC
=
arm-none-eabi-gcc
...
...
@@ -25,7 +26,7 @@ LD = arm-none-eabi-ld
OBJCOPY
=
arm-none-eabi-objcopy
SIZE
=
arm-none-eabi-size
CFLAGS_CORTEX_M4
=
-mthumb
-mtune
=
cortex-m4
-mabi
=
aapcs-linux
-mcpu
=
cortex-m4
-mfpu
=
fpv4-sp-d16
-mfloat-abi
=
hard
-fsingle-precision-constant
-Wdouble-promotion
-DSTM32F40_41xxx
-DUSE_STDPERIPH_DRIVER
-DHSE_VALUE
=
8000000
CFLAGS_CORTEX_M4
=
-mthumb
-mtune
=
cortex-m4
-mabi
=
aapcs-linux
-mcpu
=
cortex-m4
-mfpu
=
fpv4-sp-d16
-mfloat-abi
=
hard
-fsingle-precision-constant
-Wdouble-promotion
-DSTM32F40_41xxx
-DUSE_STDPERIPH_DRIVER
-DHSE_VALUE
=
$(OSC_VALUE)
CFLAGS
=
-I
.
-I
$(PY_SRC)
-I
$(FATFSSRC)
-I
$(CMSIS)
-I
$(STMSRC)
-Wall
-ansi
-std
=
gnu99
$(CFLAGS_CORTEX_M4)
-D
$(TARGET)
#CFLAGS += -I$(STMOTGSRC) -DUSE_HOST_MODE -DUSE_OTG_MODE
...
...
stm/system_stm32f4xx.c
View file @
8517bce6
...
...
@@ -54,9 +54,9 @@
*-----------------------------------------------------------------------------
* APB2 Prescaler | 2
*-----------------------------------------------------------------------------
* HSE Frequency(Hz) |
8000000 changed dpgeorge
* HSE Frequency(Hz) |
HSE_VALUE
*-----------------------------------------------------------------------------
* PLL_M |
8 changed dpgeorge
* PLL_M |
(HSE_VALUE/1000000)
*-----------------------------------------------------------------------------
* PLL_N | 336
*-----------------------------------------------------------------------------
...
...
@@ -251,7 +251,7 @@
/************************* PLL Parameters *************************************/
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
#define PLL_M
8
#define PLL_M
(HSE_VALUE/1000000)
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
#define PLL_Q 7
...
...
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