Commit 3ef91134 authored by Damien George's avatar Damien George
Browse files

stmhal: Update STM32Cube F4 HAL driver to V1.3.0.

This patch updates ST's HAL to the latest version, V1.3.0, dated 19 June
2014.  Files were copied verbatim from the ST package.  Only change was
to suppress compiler warning of unused variables in 4 places.

A lot of the changes from ST are cosmetic: comments and white space.
Some small code changes here and there, and addition of F411 header.

Main code change is how SysTick interrupt is set: it now has a
configuration variable to set the priority, so we no longer need to work
around this (originall in system_stm32f4xx.c).
parent 8a11d693
......@@ -129,6 +129,7 @@ SRC_HAL = $(addprefix $(HAL_DIR)/src/,\
stm32f4xx_hal_gpio.c \
stm32f4xx_hal_i2c.c \
stm32f4xx_hal_pcd.c \
stm32f4xx_hal_pcd_ex.c \
stm32f4xx_hal_rcc.c \
stm32f4xx_hal_rcc_ex.c \
stm32f4xx_hal_rng.c \
......
This diff is collapsed.
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_conf.h
* @author MCD Application Team
* @version V1.0.1
* @date 26-February-2014
* @version V1.1.0
* @date 19-June-2014
* @brief HAL configuration file.
******************************************************************************
* @attention
......@@ -117,6 +117,21 @@
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)40000)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
......@@ -134,6 +149,7 @@
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0x00) /*!< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define INSTRUCTION_CACHE_ENABLE 1
......@@ -380,8 +396,7 @@
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
......
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_conf.h
* @author MCD Application Team
* @version V1.0.1
* @date 26-February-2014
* @version V1.1.0
* @date 19-June-2014
* @brief HAL configuration file.
******************************************************************************
* @attention
......@@ -116,6 +116,21 @@
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)40000)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
......@@ -133,6 +148,7 @@
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0x00) /*!< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define INSTRUCTION_CACHE_ENABLE 1
......@@ -379,8 +395,7 @@
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
......
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_conf.h
* @author MCD Application Team
* @version V1.0.1
* @date 26-February-2014
* @version V1.1.0
* @date 19-June-2014
* @brief HAL configuration file.
******************************************************************************
* @attention
......@@ -116,6 +116,21 @@
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)40000)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
......@@ -133,6 +148,7 @@
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0x00) /*!< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define INSTRUCTION_CACHE_ENABLE 1
......@@ -379,8 +395,7 @@
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
......
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_conf.h
* @author MCD Application Team
* @version V1.0.1
* @date 26-February-2014
* @version V1.1.0
* @date 19-June-2014
* @brief HAL configuration file.
******************************************************************************
* @attention
......@@ -116,6 +116,21 @@
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)40000)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
......@@ -133,6 +148,7 @@
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0x00) /*!< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define INSTRUCTION_CACHE_ENABLE 1
......@@ -379,8 +395,7 @@
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
......
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hal_conf.h
* @author MCD Application Team
* @version V1.0.1
* @date 26-February-2014
* @version V1.1.0
* @date 19-June-2014
* @brief HAL configuration file.
******************************************************************************
* @attention
......@@ -116,6 +116,21 @@
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)40000)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
......@@ -133,6 +148,7 @@
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0x00) /*!< tick interrupt priority */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define INSTRUCTION_CACHE_ENABLE 1
......@@ -379,8 +395,7 @@
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
......
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f401xc.h
* @author MCD Application Team
* @version V2.0.0
* @date 18-February-2014
* @version V2.1.0
* @date 19-June-2014
* @brief CMSIS STM32F401xCxx Device Peripheral Access Layer Header File.
*
* This file contains:
......@@ -536,20 +536,6 @@ typedef struct
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef;
/**
* @brief RNG
*/
typedef struct
{
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
} RNG_TypeDef;
/**
* @brief __USB_OTG_Core_register
......@@ -689,6 +675,7 @@ USB_OTG_HostChannelTypeDef;
#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
#define FLASH_END ((uint32_t)0x0803FFFF) /*!< FLASH end address */
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
......@@ -763,9 +750,6 @@ USB_OTG_HostChannelTypeDef;
#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
/*!< AHB2 peripherals */
#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
/* Debug MCU registers base address */
#define DBGMCU_BASE ((uint32_t )0xE0042000)
......@@ -847,8 +831,7 @@ USB_OTG_HostChannelTypeDef;
#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
#define RNG ((RNG_TypeDef *) RNG_BASE)
#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
......@@ -1971,6 +1954,24 @@ USB_OTG_HostChannelTypeDef;
#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
/******************************************************************************/
/* */
......@@ -2121,6 +2122,9 @@ USB_OTG_HostChannelTypeDef;
#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
#define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
#define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main Regulator Low Voltage in Deep Sleep mode */
#define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
......@@ -2335,7 +2339,6 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
/******************** Bit definition for RCC_AHB3RSTR register **************/
......@@ -2384,7 +2387,6 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
/******************** Bit definition for RCC_AHB2ENR register ***************/
#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
/******************** Bit definition for RCC_AHB3ENR register ***************/
......@@ -2433,7 +2435,6 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
/******************** Bit definition for RCC_AHB2LPENR register *************/
#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
/******************** Bit definition for RCC_AHB3LPENR register *************/
......@@ -2513,22 +2514,6 @@ USB_OTG_HostChannelTypeDef;
#define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
#define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
/******************************************************************************/
/* */
/* RNG */
/* */
/******************************************************************************/
/******************** Bits definition for RNG_CR register *******************/
#define RNG_CR_RNGEN ((uint32_t)0x00000004)
#define RNG_CR_IE ((uint32_t)0x00000008)
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY ((uint32_t)0x00000001)
#define RNG_SR_CECS ((uint32_t)0x00000002)
#define RNG_SR_SECS ((uint32_t)0x00000004)
#define RNG_SR_CEIS ((uint32_t)0x00000020)
#define RNG_SR_SEIS ((uint32_t)0x00000040)
/******************************************************************************/
/* */
/* Real-Time Clock (RTC) */
......@@ -3166,10 +3151,7 @@ USB_OTG_HostChannelTypeDef;
#define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
/****************** Bit definition for SYSCFG_PMC register ******************/
#define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */
#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
#define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */
#define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */
/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
......@@ -4538,9 +4520,6 @@ USB_OTG_HostChannelTypeDef;
((INSTANCE) == I2S2ext) || \
((INSTANCE) == I2S3ext))
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
......
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f401xe.h
* @author MCD Application Team
* @version V2.0.0
* @date 18-February-2014
* @version V2.1.0
* @date 19-June-2014
* @brief CMSIS STM32F401xExx Device Peripheral Access Layer Header File.
*
* This file contains:
......@@ -537,20 +537,6 @@ typedef struct
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef;
/**
* @brief RNG
*/
typedef struct
{
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
} RNG_TypeDef;
/**
* @brief __USB_OTG_Core_register
*/
......@@ -689,6 +675,7 @@ USB_OTG_HostChannelTypeDef;
#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
#define FLASH_END ((uint32_t)0x0807FFFF) /*!< FLASH end address */
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
......@@ -763,9 +750,6 @@ USB_OTG_HostChannelTypeDef;
#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)
#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)
/*!< AHB2 peripherals */
#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
/* Debug MCU registers base address */
#define DBGMCU_BASE ((uint32_t )0xE0042000)
......@@ -847,8 +831,7 @@ USB_OTG_HostChannelTypeDef;
#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
#define RNG ((RNG_TypeDef *) RNG_BASE)
#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
......@@ -1971,6 +1954,24 @@ USB_OTG_HostChannelTypeDef;
#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
/****************** Bit definition for GPIO_LCKR register ********************/
#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
/******************************************************************************/
/* */
......@@ -2121,7 +2122,10 @@ USB_OTG_HostChannelTypeDef;
#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */
#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
#define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low Power Regulator Low Voltage in Deep Sleep mode */
#define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main Regulator Low Voltage in Deep Sleep mode */
#define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */
#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */
#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */
......@@ -2335,7 +2339,6 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)
#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)
/******************** Bit definition for RCC_AHB3RSTR register **************/
......@@ -2384,7 +2387,6 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)
/******************** Bit definition for RCC_AHB2ENR register ***************/
#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)
#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)
/******************** Bit definition for RCC_AHB3ENR register ***************/
......@@ -2433,7 +2435,6 @@ USB_OTG_HostChannelTypeDef;
#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)
/******************** Bit definition for RCC_AHB2LPENR register *************/
#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)
#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)
/******************** Bit definition for RCC_AHB3LPENR register *************/
......@@ -2513,22 +2514,6 @@ USB_OTG_HostChannelTypeDef;
#define RCC_PLLI2SCFGR_PLLI2SR_1 ((uint32_t)0x20000000)
#define RCC_PLLI2SCFGR_PLLI2SR_2 ((uint32_t)0x40000000)
/******************************************************************************/
/* */
/* RNG */
/* */
/******************************************************************************/
/******************** Bits definition for RNG_CR register *******************/
#define RNG_CR_RNGEN ((uint32_t)0x00000004)
#define RNG_CR_IE ((uint32_t)0x00000008)
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY ((uint32_t)0x00000001)
#define RNG_SR_CECS ((uint32_t)0x00000002)
#define RNG_SR_SECS ((uint32_t)0x00000004)
#define RNG_SR_CEIS ((uint32_t)0x00000020)
#define RNG_SR_SEIS ((uint32_t)0x00000040)
/******************************************************************************/
/* */
/* Real-Time Clock (RTC) */
......@@ -3166,10 +3151,7 @@ USB_OTG_HostChannelTypeDef;
#define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)
/****************** Bit definition for SYSCFG_PMC register ******************/
#define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */
#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */
#define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */
#define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */
/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x000F) /*!<EXTI 0 configuration */
......@@ -4538,9 +4520,6 @@ USB_OTG_HostChannelTypeDef;
((INSTANCE) == I2S2ext) || \
((INSTANCE) == I2S3ext))
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
......
......@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f405xx.h
* @author MCD Application Team
* @version V2.0.0
* @date 18-February-2014
* @version V2.1.0
* @date 19-June-2014
* @brief CMSIS STM32F405xx Device Peripheral Access Layer Header File.
*
* This file contains:
......@@ -854,6 +854,8 @@ USB_OTG_HostChannelTypeDef;
#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
#define FLASH_END ((uint32_t)0x080FFFFF) /*!< FLASH end address */
#define CCMDATARAM_END ((uint32_t)0x1000FFFF) /*!< CCM data RAM end address */
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
......@@ -4342,6 +4344,24 @@ USB_OTG_HostChannelTypeDef;
#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
/******************************************************************************/
/* */
......@@ -7292,6 +7312,19 @@ USB_OTG_HostChannelTypeDef;
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
/******************************************************************************/
/* For a painless codes migration between the STM32F4xx device product */
/* lines, the aliases defined below are put in place to overcome the */
/* differences in the interrupt handlers and IRQn definitions. */
/* No need to update developed interrupt code when moving across */
/* product lines within the same STM32F4 Family */
/******************************************************************************/
/* Aliases for __IRQn */
#define FMC_IRQn FSMC_IRQn