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TASTE
uPython-mirror
Commits
1d1e4e1b
Commit
1d1e4e1b
authored
Jan 23, 2014
by
mux
Browse files
Fix USB CORE PCGCCTL Wrong Address
* Fix PCGCCTL bug using address instead of value. * Fix issue #211
parent
638179fb
Changes
2
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Inline
Side-by-side
stm/lib/usb_core.c
View file @
1d1e4e1b
...
...
@@ -1961,7 +1961,7 @@ void USB_OTG_ActiveRemoteWakeup(USB_OTG_CORE_HANDLE *pdev)
if
(
pdev
->
cfg
.
low_power
)
{
/* un-gate USB Core clock */
power
.
d32
=
USB_OTG_READ_REG32
(
&
pdev
->
regs
.
PCGCCTL
);
// dpgeorge: taking the address here might be wrong...
power
.
d32
=
USB_OTG_READ_REG32
(
pdev
->
regs
.
PCGCCTL
);
power
.
b
.
gatehclk
=
0
;
power
.
b
.
stoppclk
=
0
;
USB_OTG_WRITE_REG32
(
pdev
->
regs
.
PCGCCTL
,
power
.
d32
);
...
...
@@ -1995,7 +1995,7 @@ void USB_OTG_UngateClock(USB_OTG_CORE_HANDLE *pdev)
if
(
dsts
.
b
.
suspsts
==
1
)
{
/* un-gate USB Core clock */
power
.
d32
=
USB_OTG_READ_REG32
(
&
pdev
->
regs
.
PCGCCTL
);
// dpgeorge: taking the address here might be wrong...
power
.
d32
=
USB_OTG_READ_REG32
(
pdev
->
regs
.
PCGCCTL
);
power
.
b
.
gatehclk
=
0
;
power
.
b
.
stoppclk
=
0
;
USB_OTG_WRITE_REG32
(
pdev
->
regs
.
PCGCCTL
,
power
.
d32
);
...
...
stm/lib/usb_dcd_int.c
View file @
1d1e4e1b
...
...
@@ -352,7 +352,7 @@ static uint32_t DCD_HandleResume_ISR(USB_OTG_CORE_HANDLE *pdev)
if
(
pdev
->
cfg
.
low_power
)
{
/* un-gate USB Core clock */
power
.
d32
=
USB_OTG_READ_REG32
(
&
pdev
->
regs
.
PCGCCTL
);
// dpgeorge: taking the address here might be wrong...
power
.
d32
=
USB_OTG_READ_REG32
(
pdev
->
regs
.
PCGCCTL
);
power
.
b
.
gatehclk
=
0
;
power
.
b
.
stoppclk
=
0
;
USB_OTG_WRITE_REG32
(
pdev
->
regs
.
PCGCCTL
,
power
.
d32
);
...
...
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