Commit 0c0550bf authored by Damien George's avatar Damien George
Browse files

drivers, wiznet5k: Add W5200 support.

parent 79d17e3e
// dpgeorge: this file taken from w5500/w5500.c and adapted to W5200
//*****************************************************************************
//
//! \file w5500.c
//! \brief W5500 HAL Interface.
//! \version 1.0.1
//! \date 2013/10/21
//! \par Revision history
//! <2014/05/01> V1.0.2
//! 1. Implicit type casting -> Explicit type casting. Refer to M20140501
//! Fixed the problem on porting into under 32bit MCU
//! Issued by Mathias ClauBen, wizwiki forum ID Think01 and bobh
//! Thank for your interesting and serious advices.
//! <2013/10/21> 1st Release
//! <2013/12/20> V1.0.1
//! 1. Remove warning
//! 2. WIZCHIP_READ_BUF WIZCHIP_WRITE_BUF in case _WIZCHIP_IO_MODE_SPI_FDM_
//! for loop optimized(removed). refer to M20131220
//! \author MidnightCow
//! \copyright
//!
//! Copyright (c) 2013, WIZnet Co., LTD.
//! All rights reserved.
//!
//! Redistribution and use in source and binary forms, with or without
//! modification, are permitted provided that the following conditions
//! are met:
//!
//! * Redistributions of source code must retain the above copyright
//! notice, this list of conditions and the following disclaimer.
//! * Redistributions in binary form must reproduce the above copyright
//! notice, this list of conditions and the following disclaimer in the
//! documentation and/or other materials provided with the distribution.
//! * Neither the name of the <ORGANIZATION> nor the names of its
//! contributors may be used to endorse or promote products derived
//! from this software without specific prior written permission.
//!
//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
//! THE POSSIBILITY OF SUCH DAMAGE.
//
//*****************************************************************************
#include "w5200.h"
#define SMASK (0x7ff) /* tx buffer mask */
#define RMASK (0x7ff) /* rx buffer mask */
#define SSIZE (2048) /* max tx buffer size */
#define RSIZE (2048) /* max rx buffer size */
#define TXBUF_BASE (0x8000)
#define RXBUF_BASE (0xc000)
#define SBASE(sn) (TXBUF_BASE + SSIZE * (sn)) /* tx buffer base for socket sn */
#define RBASE(sn) (RXBUF_BASE + RSIZE * (sn)) /* rx buffer base for socket sn */
uint8_t WIZCHIP_READ(uint32_t AddrSel) {
WIZCHIP_CRITICAL_ENTER();
WIZCHIP.CS._select();
uint8_t spi_data[4] = {
AddrSel >> 8,
AddrSel,
0x00,
0x01,
};
WIZCHIP.IF.SPI._write_bytes(spi_data, 4);
uint8_t ret;
WIZCHIP.IF.SPI._read_bytes(&ret, 1);
WIZCHIP.CS._deselect();
WIZCHIP_CRITICAL_EXIT();
return ret;
}
void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb) {
WIZCHIP_CRITICAL_ENTER();
WIZCHIP.CS._select();
uint8_t spi_data[5] = {
AddrSel >> 8,
AddrSel,
0x80,
0x01,
wb,
};
WIZCHIP.IF.SPI._write_bytes(spi_data, 5);
WIZCHIP.CS._deselect();
WIZCHIP_CRITICAL_EXIT();
}
void WIZCHIP_READ_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len) {
WIZCHIP_CRITICAL_ENTER();
WIZCHIP.CS._select();
uint8_t spi_data[4] = {
AddrSel >> 8,
AddrSel,
0x00 | ((len >> 8) & 0x7f),
len & 0xff,
};
WIZCHIP.IF.SPI._write_bytes(spi_data, 4);
WIZCHIP.IF.SPI._read_bytes(pBuf, len);
WIZCHIP.CS._deselect();
WIZCHIP_CRITICAL_EXIT();
}
void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len) {
WIZCHIP_CRITICAL_ENTER();
WIZCHIP.CS._select();
uint8_t spi_data[4] = {
AddrSel >> 8,
AddrSel,
0x80 | ((len >> 8) & 0x7f),
len & 0xff,
};
WIZCHIP.IF.SPI._write_bytes(spi_data, 4);
WIZCHIP.IF.SPI._write_bytes(pBuf, len);
WIZCHIP.CS._deselect();
WIZCHIP_CRITICAL_EXIT();
}
uint16_t getSn_TX_FSR(uint8_t sn) {
uint16_t val = 0, val1 = 0;
do {
val1 = (WIZCHIP_READ(Sn_TX_FSR(sn)) << 8) | WIZCHIP_READ(Sn_TX_FSR(sn) + 1);
if (val1 != 0) {
val = (WIZCHIP_READ(Sn_TX_FSR(sn)) << 8) | WIZCHIP_READ(Sn_TX_FSR(sn) + 1);
}
} while (val != val1);
return val;
}
uint16_t getSn_RX_RSR(uint8_t sn) {
uint16_t val = 0, val1 = 0;
do {
val1 = (WIZCHIP_READ(Sn_RX_RSR(sn)) << 8) | WIZCHIP_READ(Sn_RX_RSR(sn) + 1);
if (val1 != 0) {
val = (WIZCHIP_READ(Sn_RX_RSR(sn)) << 8) | WIZCHIP_READ(Sn_RX_RSR(sn) + 1);
}
} while (val != val1);
return val;
}
void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len) {
if (len == 0) {
return;
}
uint16_t ptr = getSn_TX_WR(sn);
uint16_t offset = ptr & SMASK;
uint32_t addr = offset + SBASE(sn);
if (offset + len > SSIZE) {
// implement wrap-around circular buffer
uint16_t size = SSIZE - offset;
WIZCHIP_WRITE_BUF(addr, wizdata, size);
WIZCHIP_WRITE_BUF(SBASE(sn), wizdata + size, len - size);
} else {
WIZCHIP_WRITE_BUF(addr, wizdata, len);
}
ptr += len;
setSn_TX_WR(sn, ptr);
}
void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len) {
if (len == 0) {
return;
}
uint16_t ptr = getSn_RX_RD(sn);
uint16_t offset = ptr & RMASK;
uint16_t addr = RBASE(sn) + offset;
if (offset + len > RSIZE) {
// implement wrap-around circular buffer
uint16_t size = RSIZE - offset;
WIZCHIP_READ_BUF(addr, wizdata, size);
WIZCHIP_READ_BUF(RBASE(sn), wizdata + size, len - size);
} else {
WIZCHIP_READ_BUF(addr, wizdata, len);
}
ptr += len;
setSn_RX_RD(sn, ptr);
}
void wiz_recv_ignore(uint8_t sn, uint16_t len) {
uint16_t ptr = getSn_RX_RD(sn);
ptr += len;
setSn_RX_RD(sn, ptr);
}
// dpgeorge: this file taken from w5500/w5500.h and adapted to W5200
//*****************************************************************************
//
//! \file w5500.h
//! \brief W5500 HAL Header File.
//! \version 1.0.0
//! \date 2013/10/21
//! \par Revision history
//! <2013/10/21> 1st Release
//! \author MidnightCow
//! \copyright
//!
//! Copyright (c) 2013, WIZnet Co., LTD.
//! All rights reserved.
//!
//! Redistribution and use in source and binary forms, with or without
//! modification, are permitted provided that the following conditions
//! are met:
//!
//! * Redistributions of source code must retain the above copyright
//! notice, this list of conditions and the following disclaimer.
//! * Redistributions in binary form must reproduce the above copyright
//! notice, this list of conditions and the following disclaimer in the
//! documentation and/or other materials provided with the distribution.
//! * Neither the name of the <ORGANIZATION> nor the names of its
//! contributors may be used to endorse or promote products derived
//! from this software without specific prior written permission.
//!
//! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
//! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
//! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
//! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
//! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
//! CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
//! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
//! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
//! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
//! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
//! THE POSSIBILITY OF SUCH DAMAGE.
//
//*****************************************************************************
#ifndef _W5200_H_
#define _W5200_H_
#include <stdint.h>
#include "../wizchip_conf.h"
//#include "board.h"
#define _W5200_IO_BASE_ 0x00000000
#define WIZCHIP_CREG_ADDR(addr) (_W5200_IO_BASE_ + (addr))
#define WIZCHIP_CH_BASE (0x4000)
#define WIZCHIP_CH_SIZE (0x100)
#define WIZCHIP_SREG_ADDR(sn, addr) (_W5200_IO_BASE_ + WIZCHIP_CH_BASE + (sn) * WIZCHIP_CH_SIZE + (addr))
//////////////////////////////
//-------------------------- defgroup ---------------------------------
/**
* @defgroup W5500 W5500
*
* @brief WHIZCHIP register defines and I/O functions of @b W5500.
*
* - @ref WIZCHIP_register : @ref Common_register_group and @ref Socket_register_group
* - @ref WIZCHIP_IO_Functions : @ref Basic_IO_function, @ref Common_register_access_function and @ref Socket_register_access_function
*/
/**
* @defgroup WIZCHIP_register WIZCHIP register
* @ingroup W5500
*
* @brief WHIZCHIP register defines register group of @b W5500.
*
* - @ref Common_register_group : Common register group
* - @ref Socket_register_group : \c SOCKET n register group
*/
/**
* @defgroup WIZCHIP_IO_Functions WIZCHIP I/O functions
* @ingroup W5500
*
* @brief This supports the basic I/O functions for @ref WIZCHIP_register.
*
* - <b> Basic I/O function </b> \n
* WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF() \n\n
*
* - @ref Common_register_group <b>access functions</b> \n
* -# @b Mode \n
* getMR(), setMR()
* -# @b Interrupt \n
* getIR(), setIR(), getIMR(), setIMR(), getSIR(), setSIR(), getSIMR(), setSIMR(), getINTLEVEL(), setINTLEVEL()
* -# <b> Network Information </b> \n
* getSHAR(), setSHAR(), getGAR(), setGAR(), getSUBR(), setSUBR(), getSIPR(), setSIPR()
* -# @b Retransmission \n
* getRCR(), setRCR(), getRTR(), setRTR()
* -# @b PPPoE \n
* getPTIMER(), setPTIMER(), getPMAGIC(), getPMAGIC(), getPSID(), setPSID(), getPHAR(), setPHAR(), getPMRU(), setPMRU()
* -# <b> ICMP packet </b>\n
* getUIPR(), getUPORTR()
* -# @b etc. \n
* getPHYCFGR(), setPHYCFGR(), getVERSIONR() \n\n
*
* - \ref Socket_register_group <b>access functions</b> \n
* -# <b> SOCKET control</b> \n
* getSn_MR(), setSn_MR(), getSn_CR(), setSn_CR(), getSn_IMR(), setSn_IMR(), getSn_IR(), setSn_IR()
* -# <b> SOCKET information</b> \n
* getSn_SR(), getSn_DHAR(), setSn_DHAR(), getSn_PORT(), setSn_PORT(), getSn_DIPR(), setSn_DIPR(), getSn_DPORT(), setSn_DPORT()
* getSn_MSSR(), setSn_MSSR()
* -# <b> SOCKET communication </b> \n
* getSn_RXBUF_SIZE(), setSn_RXBUF_SIZE(), getSn_TXBUF_SIZE(), setSn_TXBUF_SIZE() \n
* getSn_TX_RD(), getSn_TX_WR(), setSn_TX_WR() \n
* getSn_RX_RD(), setSn_RX_RD(), getSn_RX_WR() \n
* getSn_TX_FSR(), getSn_RX_RSR(), getSn_KPALVTR(), setSn_KPALVTR()
* -# <b> IP header field </b> \n
* getSn_FRAG(), setSn_FRAG(), getSn_TOS(), setSn_TOS() \n
* getSn_TTL(), setSn_TTL()
*/
/**
* @defgroup Common_register_group Common register
* @ingroup WIZCHIP_register
*
* @brief Common register group\n
* It set the basic for the networking\n
* It set the configuration such as interrupt, network information, ICMP, etc.
* @details
* @sa MR : Mode register.
* @sa GAR, SUBR, SHAR, SIPR
* @sa INTLEVEL, IR, IMR, SIR, SIMR : Interrupt.
* @sa RTR, RCR : Data retransmission.
* @sa PTIMER, PMAGIC, PHAR, PSID, PMRU : PPPoE.
* @sa UIPR, UPORTR : ICMP message.
* @sa PHYCFGR, VERSIONR : etc.
*/
/**
* @defgroup Socket_register_group Socket register
* @ingroup WIZCHIP_register
*
* @brief Socket register group.\n
* Socket register configures and control SOCKETn which is necessary to data communication.
* @details
* @sa Sn_MR, Sn_CR, Sn_IR, Sn_IMR : SOCKETn Control
* @sa Sn_SR, Sn_PORT, Sn_DHAR, Sn_DIPR, Sn_DPORT : SOCKETn Information
* @sa Sn_MSSR, Sn_TOS, Sn_TTL, Sn_KPALVTR, Sn_FRAG : Internet protocol.
* @sa Sn_RXBUF_SIZE, Sn_TXBUF_SIZE, Sn_TX_FSR, Sn_TX_RD, Sn_TX_WR, Sn_RX_RSR, Sn_RX_RD, Sn_RX_WR : Data communication
*/
/**
* @defgroup Basic_IO_function Basic I/O function
* @ingroup WIZCHIP_IO_Functions
* @brief These are basic input/output functions to read values from register or write values to register.
*/
/**
* @defgroup Common_register_access_function Common register access functions
* @ingroup WIZCHIP_IO_Functions
* @brief These are functions to access <b>common registers</b>.
*/
/**
* @defgroup Socket_register_access_function Socket register access functions
* @ingroup WIZCHIP_IO_Functions
* @brief These are functions to access <b>socket registers</b>.
*/
//------------------------------- defgroup end --------------------------------------------
//----------------------------- W5500 Common Registers IOMAP -----------------------------
/**
* @ingroup Common_register_group
* @brief Mode Register address(R/W)\n
* @ref MR is used for S/W reset, ping block mode, PPPoE mode and etc.
* @details Each bit of @ref MR defined as follows.
* <table>
* <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr>
* <tr> <td>RST</td> <td>Reserved</td> <td>WOL</td> <td>PB</td> <td>PPPoE</td> <td>Reserved</td> <td>FARP</td> <td>Reserved</td> </tr>
* </table>
* - \ref MR_RST : Reset
* - \ref MR_WOL : Wake on LAN
* - \ref MR_PB : Ping block
* - \ref MR_PPPOE : PPPoE mode
* - \ref MR_FARP : Force ARP mode
*/
#define MR WIZCHIP_CREG_ADDR(0x0000)
/**
* @ingroup Common_register_group
* @brief Gateway IP Register address(R/W)
* @details @ref GAR configures the default gateway address.
*/
#define GAR WIZCHIP_CREG_ADDR(0x0001)
/**
* @ingroup Common_register_group
* @brief Subnet mask Register address(R/W)
* @details @ref SUBR configures the subnet mask address.
*/
#define SUBR WIZCHIP_CREG_ADDR(0x0005)
/**
* @ingroup Common_register_group
* @brief Source MAC Register address(R/W)
* @details @ref SHAR configures the source hardware address.
*/
#define SHAR WIZCHIP_CREG_ADDR(0x0009)
/**
* @ingroup Common_register_group
* @brief Source IP Register address(R/W)
* @details @ref SIPR configures the source IP address.
*/
#define SIPR WIZCHIP_CREG_ADDR(0x000f)
/**
* @ingroup Common_register_group
* @brief Set Interrupt low level timer register address(R/W)
* @details @ref INTLEVEL configures the Interrupt Assert Time.
*/
//#define INTLEVEL (_W5500_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3))
/**
* @ingroup Common_register_group
* @brief Interrupt Register(R/W)
* @details @ref IR indicates the interrupt status. Each bit of @ref IR will be still until the bit will be written to by the host.
* If @ref IR is not equal to x00 INTn PIN is asserted to low until it is x00\n\n
* Each bit of @ref IR defined as follows.
* <table>
* <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr>
* <tr> <td>CONFLICT</td> <td>UNREACH</td> <td>PPPoE</td> <td>MP</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> </tr>
* </table>
* - \ref IR_CONFLICT : IP conflict
* - \ref IR_UNREACH : Destination unreachable
* - \ref IR_PPPoE : PPPoE connection close
* - \ref IR_MP : Magic packet
*/
#define IR WIZCHIP_CREG_ADDR(0x0015)
/**
* @ingroup Common_register_group
* @brief Interrupt mask register(R/W)
* @details @ref IMR is used to mask interrupts. Each bit of @ref IMR corresponds to each bit of @ref IR.
* When a bit of @ref IMR is and the corresponding bit of @ref IR is an interrupt will be issued. In other words,
* if a bit of @ref IMR is an interrupt will not be issued even if the corresponding bit of @ref IR is \n\n
* Each bit of @ref IMR defined as the following.
* <table>
* <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr>
* <tr> <td>IM_IR7</td> <td>IM_IR6</td> <td>IM_IR5</td> <td>IM_IR4</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> <td>Reserved</td> </tr>
* </table>
* - \ref IM_IR7 : IP Conflict Interrupt Mask
* - \ref IM_IR6 : Destination unreachable Interrupt Mask
* - \ref IM_IR5 : PPPoE Close Interrupt Mask
* - \ref IM_IR4 : Magic Packet Interrupt Mask
*/
#define IMR WIZCHIP_CREG_ADDR(0x0016)
/**
* @ingroup Common_register_group
* @brief Socket Interrupt Register(R/W)
* @details @ref SIR indicates the interrupt status of Socket.\n
* Each bit of @ref SIR be still until @ref Sn_IR is cleared by the host.\n
* If @ref Sn_IR is not equal to x00 the n-th bit of @ref SIR is and INTn PIN is asserted until @ref SIR is x00 */
//#define SIR (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3))
/**
* @ingroup Common_register_group
* @brief Socket Interrupt Mask Register(R/W)
* @details Each bit of @ref SIMR corresponds to each bit of @ref SIR.
* When a bit of @ref SIMR is and the corresponding bit of @ref SIR is Interrupt will be issued.
* In other words, if a bit of @ref SIMR is an interrupt will be not issued even if the corresponding bit of @ref SIR is
*/
//#define SIMR (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3))
/**
* @ingroup Common_register_group
* @brief Timeout register address( 1 is 100us )(R/W)
* @details @ref RTR configures the retransmission timeout period. The unit of timeout period is 100us and the default of @ref RTR is x07D0or 000
* And so the default timeout period is 200ms(100us X 2000). During the time configured by @ref RTR, W5500 waits for the peer response
* to the packet that is transmitted by \ref Sn_CR (CONNECT, DISCON, CLOSE, SEND, SEND_MAC, SEND_KEEP command).
* If the peer does not respond within the @ref RTR time, W5500 retransmits the packet or issues timeout.
*/
#define RTR WIZCHIP_CREG_ADDR(0x0017)
/**
* @ingroup Common_register_group
* @brief Retry count register(R/W)
* @details @ref RCR configures the number of time of retransmission.
* When retransmission occurs as many as ref RCR+1 Timeout interrupt is issued (@ref Sn_IR[TIMEOUT] = .
*/
#define RCR WIZCHIP_CREG_ADDR(0x0019)
/**
* @ingroup Common_register_group
* @brief PPP LCP Request Timer register in PPPoE mode(R/W)
* @details @ref PTIMER configures the time for sending LCP echo request. The unit of time is 25ms.
*/
#define PTIMER WIZCHIP_CREG_ADDR(0x0028)
/**
* @ingroup Common_register_group
* @brief PPP LCP Magic number register in PPPoE mode(R/W)
* @details @ref PMAGIC configures the 4bytes magic number to be used in LCP negotiation.
*/
#define PMAGIC WIZCHIP_CREG_ADDR(0x0029)
/**
* @ingroup Common_register_group
* @brief PPP Destination MAC Register address(R/W)
* @details @ref PHAR configures the PPPoE server hardware address that is acquired during PPPoE connection process.
*/
//#define PHAR (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3))
/**
* @ingroup Common_register_group
* @brief PPP Session Identification Register(R/W)
* @details @ref PSID configures the PPPoE sever session ID acquired during PPPoE connection process.
*/
//#define PSID (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3))
/**
* @ingroup Common_register_group
* @brief PPP Maximum Segment Size(MSS) register(R/W)
* @details @ref PMRU configures the maximum receive unit of PPPoE.
*/
//#define PMRU (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3))
/**
* @ingroup Common_register_group
* @brief Unreachable IP register address in UDP mode(R)
* @details W5500 receives an ICMP packet(Destination port unreachable) when data is sent to a port number
* which socket is not open and @ref UNREACH bit of @ref IR becomes and @ref UIPR & @ref UPORTR indicates
* the destination IP address & port number respectively.
*/
//#define UIPR (_W5500_IO_BASE_ + (0x002a << 8) + (WIZCHIP_CREG_BLOCK << 3))
/**
* @ingroup Common_register_group
* @brief Unreachable Port register address in UDP mode(R)
* @details W5500 receives an ICMP packet(Destination port unreachable) when data is sent to a port number
* which socket is not open and @ref UNREACH bit of @ref IR becomes and @ref UIPR & @ref UPORTR
* indicates the destination IP address & port number respectively.
*/
//#define UPORTR (_W5500_IO_BASE_ + (0x002e << 8) + (WIZCHIP_CREG_BLOCK << 3))
/**
* @ingroup Common_register_group
* @brief PHY Status Register(R/W)
* @details @ref PHYCFGR configures PHY operation mode and resets PHY. In addition, @ref PHYCFGR indicates the status of PHY such as duplex, Speed, Link.
*/
//#define PHYCFGR (_W5500_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3))
#define PHYSTATUS WIZCHIP_CREG_ADDR(0x0035)
// Reserved (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_CREG_BLOCK << 3))
// Reserved (_W5500_IO_BASE_ + (0x0030 << 8) + (WIZCHIP_CREG_BLOCK << 3))
// Reserved (_W5500_IO_BASE_ + (0x0031 << 8) + (WIZCHIP_CREG_BLOCK << 3))
// Reserved (_W5500_IO_BASE_ + (0x0032 << 8) + (WIZCHIP_CREG_BLOCK << 3))
// Reserved (_W5500_IO_BASE_ + (0x0033 << 8) + (WIZCHIP_CREG_BLOCK << 3))
// Reserved (_W5500_IO_BASE_ + (0x0034 << 8) + (WIZCHIP_CREG_BLOCK << 3))
// Reserved (_W5500_IO_BASE_ + (0x0035 << 8) + (WIZCHIP_CREG_BLOCK << 3))
// Reserved (_W5500_IO_BASE_ + (0x0036 << 8) + (WIZCHIP_CREG_BLOCK << 3))
// Reserved (_W5500_IO_BASE_ + (0x0037 << 8) + (WIZCHIP_CREG_BLOCK << 3))
// Reserved (_W5500_IO_BASE_ + (0x0038 << 8) + (WIZCHIP_CREG_BLOCK << 3))
/**
* @ingroup Common_register_group
* @brief chip version register address(R)
* @details @ref VERSIONR always indicates the W5500 version as @b 0x04.
*/
//#define VERSIONR (_W5200_IO_BASE_ + (0x0039 << 8) + (WIZCHIP_CREG_BLOCK << 3))
//----------------------------- W5500 Socket Registers IOMAP -----------------------------
/**
* @ingroup Socket_register_group
* @brief socket Mode register(R/W)
* @details @ref Sn_MR configures the option or protocol type of Socket n.\n\n
* Each bit of @ref Sn_MR defined as the following.
* <table>
* <tr> <td>7</td> <td>6</td> <td>5</td> <td>4</td> <td>3</td> <td>2</td> <td>1</td> <td>0</td> </tr>
* <tr> <td>MULTI/MFEN</td> <td>BCASTB</td> <td>ND/MC/MMB</td> <td>UCASTB/MIP6B</td> <td>Protocol[3]</td> <td>Protocol[2]</td> <td>Protocol[1]</td> <td>Protocol[0]</td> </tr>
* </table>
* - @ref Sn_MR_MULTI : Support UDP Multicasting
* - @ref Sn_MR_BCASTB : Broadcast block <b>in UDP Multicasting</b>
* - @ref Sn_MR_ND : No Delayed Ack(TCP) flag
* - @ref Sn_MR_MC : IGMP version used <b>in UDP mulitcasting</b>
* - @ref Sn_MR_MMB : Multicast Blocking <b>in @ref Sn_MR_MACRAW mode</b>
* - @ref Sn_MR_UCASTB : Unicast Block <b>in UDP Multicating</b>
* - @ref Sn_MR_MIP6B : IPv6 packet Blocking <b>in @ref Sn_MR_MACRAW mode</b>
* - <b>Protocol</b>
* <table>
* <tr> <td><b>Protocol[3]</b></td> <td><b>Protocol[2]</b></td> <td><b>Protocol[1]</b></td> <td><b>Protocol[0]</b></td> <td>@b Meaning</td> </tr>
* <tr> <td>0</td> <td>0</td> <td>0</td> <td>0</td> <td>Closed</td> </tr>
* <tr> <td>0</td> <td>0</td> <td>0</td> <td>1</td> <td>TCP</td> </tr>
* <tr> <td>0</td> <td>0</td> <td>1</td> <td>0</td> <td>UDP</td> </tr>
* <tr> <td>0</td> <td>1</td> <td>0</td> <td>0</td> <td>MACRAW</td> </tr>
* </table>
* - @ref Sn_MR_MACRAW : MAC LAYER RAW SOCK \n
* - @ref Sn_MR_UDP : UDP
* - @ref Sn_MR_TCP : TCP
* - @ref Sn_MR_CLOSE : Unused socket
* @note MACRAW mode should be only used in Socket 0.
*/
#define Sn_MR(N) WIZCHIP_SREG_ADDR(N, 0x0000)
/**
* @ingroup Socket_register_group
* @brief Socket command register(R/W)