• Paul Sokolovsky's avatar
    Makefiles: Remove duplicate object files when linking. · 0dbd928c
    Paul Sokolovsky authored
    Scenario: module1 depends on some common file from lib/, so specifies it
    in its SRC_MOD, and the same situation with module2, then common file
    from lib/ eventually ends up listed twice in $(OBJ), which leads to link
    Make is equipped to deal with such situation easily, quoting the manual:
    "The value of $^ omits duplicate prerequisites, while $+ retains them and
    preserves their order." So, just use $^ consistently in all link targets.