Commits (2)
* Objective 1: Test interface for a HW/SW Simulink block, possibly having more than one of these blocks (target ARM-Artix7).
* Objective 2: Test run-time reconfiguration.
* Status: One HW/SW Simulink block tested. Additional block to be soon added and tested. Run-time reconfiguration also to be soon added and tested. A new processor implementation added for ARM-Artix7 is being used, even if for the moment it is reusing an RTEMS/LEON ExP while the proper target RTEMS/ARM ExP is still under build and test activities (this is only temporary and very shortly will be updated). Hence generated .exe to be ignored for the moment. Automatic Vivado synthesis call is still under test and will be shortly added (hence no bit file output yet) (Orchestrator is already prepared though, just the actual Vivado call is commented). Therefore, currently the build output shall serve only as verification (consistency, etc.) of auto-generated sources, including device drivers and Vivado project, the latter being the input to the synthesis testing.