Approved by Gaisler, TAS-F, TAS-E and GMV: RDHC's library and header files...

Approved by Gaisler, TAS-F, TAS-E and GMV: RDHC's library and header files needed for use by TASTE applications.

external_libs/inc/ethernet_driver/ethernet_driver.h

+/*
+*=============================================================================
+* FILE NAME     : ethernet_tctm.h
+* AUTHOR        : E. OLIVERO
+* CREATION DATE : 24/01/2019
+*=============================================================================
+* PRODUCT       : CORAMBAD
+* MODULE        : IFDRIVERS / TCTM 
+* RULE          : ETHERNET TCTM driver interface
+* DEPENDANCIES  : Linux
+* ---------------------------------------------------------------------------
+* This document is the property of THALES ALENIA SPACE : no part of it shall
+* be reproduced or transmitted without the express prior written authorization
+* of THALES ALENIA SPACE and its contents shall not be disclosed.
+* (c) Copyright 2016, THALES ALENIA SPACE
+*=============================================================================
+*/
+
+/* Declaration of the external software environment used */
+/* ----------------------------------------------------- */
+/* To avoid double declaration */
+/* --------------------------- */
+#ifndef __INCetherneth
+#define __INCetherneth
+
+
+/*
+*   \brief int ethernet_initialise(void)
+*   \brief ETHERNET board initialisation
+*
+*   \param None
+*
+*   \return int Fd socket if open and bind successfuly else fd error
+*/
+int ethernet_init(void);
+
+/*
+*   \brief int ethernet_send(int Socket, unsigned char *pt_cltu, unsigned int lg)
+*   \brief ETHERNET send CLTU
+*
+*   \param[in] int Socket : Socket identifer
+*   \param[in] unsigned char *pt_cltu : CLTU data to send
+*   \param[in] unsigned int lg : CLTU size
+*
+*   \return int Size of send CLTU
+*/
+int ethernet_send(int Socket, unsigned char *pt_cltu, int lg);
+
+/*
+*   \brief int ethernet_receive(int Socket, u_char& *cadu_buffer, int size)
+*   \brief ETHERNET receive CLTU
+*
+*   \param[in] int Socket : Socket identifer
+*   \param[in] unsigned char *cadu_buffer : buffer to receive the received CADU
+*   \param[in] int size : CADU received size
+*
+*   \return  int Size of received CADU
+*/
+int ethernet_receive(int Socket, unsigned char *cadu_buffer, int size);
+
+/*
+*   \brief int ethernet_close(void)
+*   \ETHERNET close communication
+*
+*   \param None
+*	
+*   \return None
+*/
+void ethernet_close(int Socket);
+
+/* End of declaration */
+/* ------------------ */
+#endif
+

external_libs/inc/hdsw/bootinfo.h

+/*
+ * This source code file is part of the CORA RDHC software.
+ * Copyright (C) 2018, Cobham Gaisler AB - all rights reserved.
+ *
+ * Any use or redistribution in part or in whole must be approved in advance in
+ * writing. By default, distribution or disclosure is not permitted.
+ *
+ * The source code may be used only by ESA CORA RDHC, ESA CORA MBAD and ESA
+ * CORA SAGE contractors during the activity in ESA Contract 4000121650/NL/LF,
+ * and only for use on the CORA RDHC hardware platform (COTS or EBB).
+ *
+ * Contact Cobham Gaisler AB, sales@gaisler.com, for licensing questions.
+ */
+
+#ifndef BOOTINFO_H
+#define BOOTINFO_H
+
+#include <stdint.h>
+
+/*
+ * Entry point and stack pointer for application starting on secondary
+ * processors. Can be set from application to override ep/sp definition in ASW
+ * image.
+ */
+struct bootentry {
+        uint32_t ep;
+        uint32_t sp;
+};
+
+struct report {
+        uint32_t version;
+        uint32_t ram_addrbus;
+        uint32_t ram_seqdata;
+        uint32_t rom;
+        uint32_t l2cache;
+        uint32_t asw[16];
+        struct {
+                uint32_t iram;
+                uint32_t dram;
+        } cpu[16];
+};
+
+struct bootinfo {
+        struct bootentry bootentry[16];
+
+        /* Boot report */
+        struct report report;
+
+        /* Force assertion of external reset. */
+        void (*cold_restart)(void);
+        /*
+         * Restart boot loader. apparg is available in %g5 at entry to
+         * application.
+         */
+        void (*warm_restart)(uint32_t apparg);
+
+        /* Enter power-down in ROM and run init sequence when woken up. */
+        void (*rompark)(void);
+};
+
+extern struct bootinfo bootinfo;
+
+#endif
+

external_libs/inc/hdsw/gpio.h

+/*
+ * This source code file is part of the CORA RDHC software.
+ * Copyright (C) 2018, Cobham Gaisler AB - all rights reserved.
+ *
+ * Any use or redistribution in part or in whole must be approved in advance in
+ * writing. By default, distribution or disclosure is not permitted.
+ *
+ * The source code may be used only by ESA CORA RDHC, ESA CORA MBAD and ESA
+ * CORA SAGE contractors during the activity in ESA Contract 4000121650/NL/LF,
+ * and only for use on the CORA RDHC hardware platform (COTS or EBB).
+ *
+ * Contact Cobham Gaisler AB, sales@gaisler.com, for licensing questions.
+ */
+
+#ifndef _GPIO_H_
+#define _GPIO_H_
+
+/*
+ * HDSW driver for GRGPIO
+ *
+ * The main mechanics of this driver consist in managing GRGPIO device
+ * open/close operations. Actual GPIO operations exported to the
+ * user are highly connected on how the hardware registers work. Register
+ * manipulation should be done with constants defined in the file
+ * regs/grgpio-regs.h.
+ */
+
+#include <stdint.h>
+
+struct gpio_regs_cfg {
+	uint32_t addr;
+	/* Mask representing the implemented GPIO */
+	uint32_t mask;
+};
+
+/*** Device interface ***/
+
+/* Retrieve number of GRGPIO devices registered to the driver. */
+int gpio_dev_count(void);
+
+/*
+ * Open a GPIO device.
+ *
+ * - All GPIO ports are configured as inputs
+ * - Interrupts are disabled.
+ * - Internal data structures are initialized.
+ * - Device is marked opened.
+ * return: device handle
+ */
+void *gpio_open(int dev_no);
+
+/* d: device handle
+ * return: DRV_OK
+ */
+int gpio_close(void *d);
+
+/** Device register access **/
+
+/*
+ * d: device handle
+ * return: Register content before newval is written
+ */
+uint32_t gpio_data(void *d);
+
+/*
+ * d: device handle
+ * set: 0 - do not write register, others - write register
+ * newval: value to write to register
+ * return: Register content before newval is written
+ */
+uint32_t gpio_output(void *d, int set, uint32_t newval);
+uint32_t gpio_direction(void *d, int set, uint32_t newval);
+uint32_t gpio_intmask(void *d, int set, uint32_t newval);
+uint32_t gpio_intpol(void *d, int set, uint32_t newval);
+uint32_t gpio_intedge(void *d, int set, uint32_t newval);
+uint32_t gpio_iflag(void *d, int set, uint32_t newval);
+uint32_t gpio_pulse(void *d, int set, uint32_t newval);
+uint32_t gpio_irqmap(void *d, int i, int set, uint32_t newval);
+
+int gpio_output_or (void *d, uint32_t mask);
+int gpio_output_and(void *d, uint32_t mask);
+int gpio_direction_or (void *d, uint32_t mask);
+int gpio_direction_and(void *d, uint32_t mask);
+int gpio_intmask_or (void *d, uint32_t mask);
+int gpio_intmask_and(void *d, uint32_t mask);
+
+#endif
+

external_libs/inc/hdsw/grspw_pkt_lib.h

+/*
+ * This source code file is part of the CORA RDHC software.
+ * Copyright (C) 2018, Cobham Gaisler AB - all rights reserved.
+ *
+ * Any use or redistribution in part or in whole must be approved in advance in
+ * writing. By default, distribution or disclosure is not permitted.
+ *
+ * The source code may be used only by ESA CORA RDHC, ESA CORA MBAD and ESA
+ * CORA SAGE contractors during the activity in ESA Contract 4000121650/NL/LF,
+ * and only for use on the CORA RDHC hardware platform (COTS or EBB).
+ *
+ * Contact Cobham Gaisler AB, sales@gaisler.com, for licensing questions.
+ */
+
+/* GRSPW Packet driver Library helper functions */
+
+#ifndef __GRSPW_PKT_LIB_H__
+#define __GRSPW_PKT_LIB_H__
+
+#include <bsp/grspw_pkt.h>
+
+/* GRSPW Device handles and DMA handles */
+struct grspw_dev {
+	void *dh;
+	void *dma[4];
+	int index;
+	struct grspw_hw_sup hwsup;
+};
+
+/* Driver configuration options described in memory */
+struct grspw_config {
+	struct grspw_addr_config adrcfg;
+	int rmap_cfg;
+	unsigned char rmap_dstkey;
+	int tc_cfg;
+	void (*tc_isr_callback)(void *data, int tc);
+	void *tc_isr_arg;
+	/* Mask of which DMA Channels to enable. Most often only
+	 * one DMA Channel is available, then set this to 1.
+	 *
+	 * By enabling a DMA Channel, the DMA Channels will be
+	 * able to receive SpaceWire packets after SpaceWire buffers 
+	 * has been prepared for it, and transmitt SpaceWire packets
+	 * when the user request transmission of a SpaceWire packet.
+	 */
+	unsigned int enable_chan_mask;
+	/* Per Channel Configuration */
+	struct grspw_dma_config chan[4];
+	/* SpW Interrupt configuration */
+	struct spwpkt_ic_config iccfg;
+};
+
+/* Statisics and diagnostics gathered by driver */
+struct grspw_stats {
+	/* Statistics for the Core */
+	struct grspw_core_stats stats;
+
+	/* Per DMA channel statistics */
+	struct grspw_dma_stats chan[4];
+};
+
+/* Current state of configuration and link */
+struct grspw_link_state {
+	int link_ctrl;			/* Link Configuration */
+	unsigned char clkdiv_start;	/* Clock Division during startup (not 
+					 * in state run) */
+	unsigned char clkdiv_run;	/* Clock Division in run-state */
+	spw_link_state_t link_state;	/* State (Error-Reset, Error-wait...) */
+	int port_cfg;			/* Port Configuration */
+	int port_active;		/* Currently active port */
+};
+
+/* Read the current driver configuration to memory */
+void grspw_config_read(struct grspw_dev *dev, struct grspw_config *cfg);
+
+/* Read the current link state from hardware */
+void grspw_link_state_get(struct grspw_dev *dev, struct grspw_link_state *state);
+
+/* Print the link state on the stdout */
+void grspw_linkstate_print(struct grspw_link_state *ls);
+
+/* Print hardware configuration from memory onto stdout */
+void grspw_cfg_print(struct grspw_hw_sup *hw, struct grspw_config *cfg);
+
+/* Copy current driver statistics to memory */
+void grspw_stats_get(struct grspw_dev *dev, struct grspw_stats *stats);
+
+/* Print GRSPW driver statistics from memory description onto stdout */
+void grspw_stats_print(struct grspw_dev *dev, struct grspw_stats *stats);
+
+/* Configure Core and DMA Channels, RMAP and TimeCode setup */
+int grspw_cfg_set(struct grspw_dev *dev, struct grspw_config *cfg);
+
+/* Start DMA operation on all open DMA channels */
+int grspw_start(struct grspw_dev *dev);
+
+/* Stop all DMA activity on all DMA channels */
+void grspw_stop(struct grspw_dev *dev);
+
+#endif /* __GRSPW_PKT_LIB_H__ */

external_libs/inc/hdsw/osal.h

+/*
+ * This source code file is part of the CORA RDHC software.
+ * Copyright (C) 2018, Cobham Gaisler AB - all rights reserved.
+ *
+ * Any use or redistribution in part or in whole must be approved in advance in
+ * writing. By default, distribution or disclosure is not permitted.
+ *
+ * The source code may be used only by ESA CORA RDHC, ESA CORA MBAD and ESA
+ * CORA SAGE contractors during the activity in ESA Contract 4000121650/NL/LF,
+ * and only for use on the CORA RDHC hardware platform (COTS or EBB).
+ *
+ * Contact Cobham Gaisler AB, sales@gaisler.com, for licensing questions.
+ */
+
+#ifndef _OSAL_H_
+#define _OSAL_H_
+
+#include <stdint.h>
+#include <osal_cfg.h>
+
+/*
+ * Register interrupt handler
+ *
+ * The function in parameter handler is registered as the interrupt handler for
+ * the given interrupt source. The handler is called with arg as argument.
+ * Interrupt source is enabled in the interrupt controller.
+ *
+ * source: Interrupt number.
+ * handler: Pointer to software routine to execute when the interrupt triggers.
+ * arg: Passed as parameter to handler.
+ *
+ * return:
+ * - DRV_OK: Handler installed successfully.
+ * - DRV_INVALID_SOURCE: Invalid source parameter.
+ * - DRV_FAIL: Unknown failure.
+ */
+int osal_isr_register(int source, void (*handler) (void *), void *arg);
+
+/*
+ * Unregister interrupt handler
+ *
+ * Unregister interrupt handler.  The parameters source, handler and arg must
+ * be the same as used when the handler was registered with osal_isr_register.
+ * It is only allowed to unregister an interrupt which has previously been
+ * registered with osal_isr_register.
+ *
+ * source: Interrupt number.
+ * handler: Pointer to software routine previously installed.
+ * arg: Parameter value previously installed.
+ *
+ * return:
+ * - DRV_OK: Handler successfully unregistered.
+ * - DRV_INVALID_SOURCE: Invalid source parameter. Handler is not unregistered.
+ * - DRV_FAIL: Unknown failure. Handler is not unregistered.
+ */
+int osal_isr_unregister(int source, void (*handler) (void *), void *arg);
+
+/*
+ * Atomic Load-Store Unsigned Byte
+ *
+ * Copy a byte from addr to temporary variable, then rewrite the addressed byte
+ * in memory with 0xff.
+ *
+ * In case atomic operation is required, the SPARC "ldstub" instruction can be
+ * used. Otherwise an emulating function is enough.
+ *
+ * Algorithm:
+ *   tmp := *addr;
+ *   *addr := 0xff;
+ *   return tmp;
+ *
+ * addr: Address of byte to operate on.
+ *
+ * return: Value at addr before store.
+ */
+uint8_t osal_ldstub(uint8_t *addr);
+
+#endif

external_libs/inc/hdsw/osal_cfg.h

+/*
+ * This source code file is part of the CORA RDHC software.
+ * Copyright (C) 2018, Cobham Gaisler AB - all rights reserved.
+ *
+ * Any use or redistribution in part or in whole must be approved in advance in
+ * writing. By default, distribution or disclosure is not permitted.
+ *
+ * The source code may be used only by ESA CORA RDHC, ESA CORA MBAD and ESA
+ * CORA SAGE contractors during the activity in ESA Contract 4000121650/NL/LF,
+ * and only for use on the CORA RDHC hardware platform (COTS or EBB).
+ *
+ * Contact Cobham Gaisler AB, sales@gaisler.com, for licensing questions.
+ */
+
+#ifndef __OSAL_CFG_H_
+#define __OSAL_CFG_H_
+
+typedef int osal_int_level_t;
+
+#define SPIN_DECLARE(name)
+#define SPIN_INIT(lock, name)
+#define SPIN_LOCK(lock, level)
+#define SPIN_LOCK_IRQ(lock, level)
+#define SPIN_UNLOCK(lock, level)
+#define SPIN_UNLOCK_IRQ(lock, level)
+#define SPIN_IRQFLAGS(k)
+#define SPIN_ISR_IRQFLAGS(k)
+
+#define osal_ldstub osal_bare_ldstub
+static inline uint8_t osal_bare_ldstub(uint8_t *addr)
+{
+	uint8_t prev = *addr;
+
+	*addr = 0xff;
+	return prev;
+}
+
+#endif
+

external_libs/inc/hdsw/rmap.h

+/*
+ * This source code file is part of the CORA RDHC software.
+ * Copyright (C) 2018, Cobham Gaisler AB - all rights reserved.
+ *
+ * Any use or redistribution in part or in whole must be approved in advance in
+ * writing. By default, distribution or disclosure is not permitted.
+ *
+ * The source code may be used only by ESA CORA RDHC, ESA CORA MBAD and ESA
+ * CORA SAGE contractors during the activity in ESA Contract 4000121650/NL/LF,
+ * and only for use on the CORA RDHC hardware platform (COTS or EBB).
+ *
+ * Contact Cobham Gaisler AB, sales@gaisler.com, for licensing questions.
+ */
+
+/* RMAP stack and RMAP driver interface
+ *
+ *  COPYRIGHT (c) 2009
+ *  Aeroflex Gaisler.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ */
+
+#ifndef __RMAP_H__
+#define __RMAP_H__
+
+#include <rtems.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*** RMAP Driver interface ***/
+
+#define PKT_OPTION_HDR_CRC	0x1 /* Enable Header CRC by Hardware */
+#define PKT_OPTION_DATA_CRC	0x2 /* Enable Data CRC by Hardware */
+/* skip len of header when calculating CRC by hardware */
+#define PKT_OPTION_HDR_CRC_SKIPLEN(len)	(((len) & 0xf) << 8)
+#define PKT_OPTION_HDR_CRC_SKIPLEN_MASK 0xf00
+
+/* RMAP SpW packet */
+struct rmap_spw_pkt {
+	int		options;	/* Data CRC | Header CRC */
+	int		hlen;
+	unsigned char	*hdr;
+	int		dlen;
+	unsigned char	*data;
+	int		reserved[2];	/* May be used internally by driver layer */
+};
+
+struct rmap_drv_ops {
+	int	(*init)(void *cookie);						/* Initialize driver */
+	int	(*ioctl)(void *cookie, int command, void *arg);			/* Configure driver */
+	int	(*send)(void *cookie, struct rmap_spw_pkt *pkt);		/* Schedule one packet for transmission */
+	int	(*recv)(void *cookie, struct rmap_spw_pkt *pkt);		/* Receive one packet */
+};
+
+/* RMAP driver description */
+struct rmap_drv {
+	struct rmap_drv_ops	ops;
+	void			*cookie;
+};
+
+#define RMAP_TIMEOUT_SET_RTIME 0x01
+#define RMAP_TIMEOUT_SET_WTIME 0x02
+struct rmap_drv_timeout {
+	unsigned int options;
+	unsigned int rtimeout;
+	unsigned int wtimeout;
+};
+
+/* RMAP driver ioctl commands */
+#define RMAP_DRV_IOCTL_START		1	/* Start operation, packets will be sent/received after this command */
+#define RMAP_DRV_IOCTL_STOP		2	/* Stop operation, no more packets will be sent before next START */
+#define RMAP_DRV_IOCTL_BLOCK		3	/* Set RX/TX blocking */
+#define RMAP_DRV_IOCTL_TIMEOUT		4	/* Set timeout in blocing mode */
+#define RMAP_DRV_IOCTL_GET_CAP		5	/* Get capabilities of the driver/hardware */
+#define RMAP_IOCTL_GET_CONFIG		6	/* Get Stack Configuration */
+
+/* Capabilities */
+#define DRV_CAP_HDR_CRC			0x1	/* Hardware supports HEADER CRC generation */
+#define DRV_CAP_DATA_CRC		0x2	/* Hardware supports DATA CRC generation */
+
+
+/*** RMAP Stack interface ***/
+
+/* Function that will generate path addressing.
+ *
+ * \param cookie   Identifies RMAP stack, 
+ * \param dir      Direction (0=to dst, 1=from dst)
+ * \param srcadr   Source address (the SpW address of the interface used)
+ * \param dstadr   Destination address to translate. Note that it is actually
+ *                 a "unsigned short" given here, so this is rather a Node-ID.
+ * \param buf      Where path address is put
+ * \param len      On calling it indicates max length. On return it must be set
+ *                 reflect the number of bytes was written to buf.
+ */
+typedef int (*rmap_route_t)(void *cookie, int dir, int srcadr, int dstadr, void *buf, int *len);
+
+struct rmap_config {
+	rmap_route_t	route_func;	/* Function that will generate path addressing */
+	unsigned short	spw_adr;	/* The SpW Address of the SpW interface used */
+	unsigned char	tid_msb;	/* 8 most significant bits in TID.
+					 * Set to 0xff for normal operation using
+					 * all bits in TID for sequence counting.
+					 */
+	unsigned char	drv_cap;	/* Driver capabilities */
+	char		thread_safe;	/* Set this to non-zero to enable the RMAP stack to create a
+					 * semaphore used to protect from multiple tasks entering the
+					 * transfer function(s) of the stack at the same time */
+	struct rmap_drv	*drv;		/* Driver used for transmission */
+	int		max_rx_len;	/* Maximum data length of received packets */
+	int		max_tx_len;	/* Maximum data length of transmitted packets */
+};
+
+struct rmap_command {
+	char			type;		/* READ/WRITE/MODIFY ... */
+	unsigned char		dstkey;		/* Destination key */
+	unsigned char		status;		/* Error/Status response. 0 if no response is expected */
+	unsigned short		dstadr;		/* Destination address */
+	unsigned short		tid;		/* TID assigned to packet */
+	unsigned long long	address;	/* READ/WRITE address, 32-bit + 8-bit extended */
+	union {
+		struct {
+			unsigned int length;	/* 24-bit data length */
+			unsigned char *data;	/* Data bytes, NOTE that 1 byte must be available
+						 * for the stack to write the DATA CRC in the end
+						 * of the data buffer. Stack write data[length] = CRC
+						 */
+		} write;
+		struct {
+			unsigned int length;	/* 24-bit length */
+			unsigned int datalength;/* Response 24-bit length, may be different from requested length */
+			unsigned int *data;	/* Response data is stored in this buffer */
+		} read;
+		struct {
+			unsigned int length;	/* length 1,2 or 4 valid */
+			unsigned int data;	/* 1,2 or 4 bytes data */
+			unsigned int mask;	/* 1,2 or 4 bytes data mask */
+			unsigned int oldlength;	/* Response, old data length */
+			unsigned int olddata;	/* Response, old data before write */
+		} read_m_write;
+	} data;
+};
+
+struct rmap_command_write {
+	char			type;		/* WRITE (Increment, Single, ACK, Verify) */
+	unsigned char		dstkey;		/* Destination key */
+	unsigned char		status;		/* Status response, set if ACK, non-zero indicates error */
+	unsigned short		dstadr;		/* Destination address */
+	unsigned short		tid;		/* TID assigned to packet */
+	unsigned long long	address;	/* READ/WRITE address */
+	unsigned int 		length;		/* 24-bit data length */
+	unsigned char		*data;		/* Data bytes, NOTE that 1 byte must be available 
+						 * for the stack to write the DATA CRC in the end 
+						 * of the data buffer. Stack write data[length] = CRC