Commit d3bac43f authored by Thanassis Tsiodras's avatar Thanassis Tsiodras

Approved by Gaisler, TAS-F, TAS-E and GMV: RDHC's library and header files...

Approved by Gaisler, TAS-F, TAS-E and GMV: RDHC's library and header files needed for use by TASTE applications.
parent 46ccd9eb
/*
*=============================================================================
* FILE NAME : ethernet_tctm.h
* AUTHOR : E. OLIVERO
* CREATION DATE : 24/01/2019
*=============================================================================
* PRODUCT : CORAMBAD
* MODULE : IFDRIVERS / TCTM
* RULE : ETHERNET TCTM driver interface
* DEPENDANCIES : Linux
* ---------------------------------------------------------------------------
* This document is the property of THALES ALENIA SPACE : no part of it shall
* be reproduced or transmitted without the express prior written authorization
* of THALES ALENIA SPACE and its contents shall not be disclosed.
* (c) Copyright 2016, THALES ALENIA SPACE
*=============================================================================
*/
/* Declaration of the external software environment used */
/* ----------------------------------------------------- */
/* To avoid double declaration */
/* --------------------------- */
#ifndef __INCetherneth
#define __INCetherneth
/*
* \brief int ethernet_initialise(void)
* \brief ETHERNET board initialisation
*
* \param None
*
* \return int Fd socket if open and bind successfuly else fd error
*/
int ethernet_init(void);
/*
* \brief int ethernet_send(int Socket, unsigned char *pt_cltu, unsigned int lg)
* \brief ETHERNET send CLTU
*
* \param[in] int Socket : Socket identifer
* \param[in] unsigned char *pt_cltu : CLTU data to send
* \param[in] unsigned int lg : CLTU size
*
* \return int Size of send CLTU
*/
int ethernet_send(int Socket, unsigned char *pt_cltu, int lg);
/*
* \brief int ethernet_receive(int Socket, u_char& *cadu_buffer, int size)
* \brief ETHERNET receive CLTU
*
* \param[in] int Socket : Socket identifer
* \param[in] unsigned char *cadu_buffer : buffer to receive the received CADU
* \param[in] int size : CADU received size
*
* \return int Size of received CADU
*/
int ethernet_receive(int Socket, unsigned char *cadu_buffer, int size);
/*
* \brief int ethernet_close(void)
* \ETHERNET close communication
*
* \param None
*
* \return None
*/
void ethernet_close(int Socket);
/* End of declaration */
/* ------------------ */
#endif
/*
* This source code file is part of the CORA RDHC software.
* Copyright (C) 2018, Cobham Gaisler AB - all rights reserved.
*
* Any use or redistribution in part or in whole must be approved in advance in
* writing. By default, distribution or disclosure is not permitted.
*
* The source code may be used only by ESA CORA RDHC, ESA CORA MBAD and ESA
* CORA SAGE contractors during the activity in ESA Contract 4000121650/NL/LF,
* and only for use on the CORA RDHC hardware platform (COTS or EBB).
*
* Contact Cobham Gaisler AB, sales@gaisler.com, for licensing questions.
*/
#ifndef BOOTINFO_H
#define BOOTINFO_H
#include <stdint.h>
/*
* Entry point and stack pointer for application starting on secondary
* processors. Can be set from application to override ep/sp definition in ASW
* image.
*/
struct bootentry {
uint32_t ep;
uint32_t sp;
};
struct report {
uint32_t version;
uint32_t ram_addrbus;
uint32_t ram_seqdata;
uint32_t rom;
uint32_t l2cache;
uint32_t asw[16];
struct {
uint32_t iram;
uint32_t dram;
} cpu[16];
};
struct bootinfo {
struct bootentry bootentry[16];
/* Boot report */
struct report report;
/* Force assertion of external reset. */
void (*cold_restart)(void);
/*
* Restart boot loader. apparg is available in %g5 at entry to
* application.
*/
void (*warm_restart)(uint32_t apparg);
/* Enter power-down in ROM and run init sequence when woken up. */
void (*rompark)(void);
};
extern struct bootinfo bootinfo;
#endif
/*
* This source code file is part of the CORA RDHC software.
* Copyright (C) 2018, Cobham Gaisler AB - all rights reserved.
*
* Any use or redistribution in part or in whole must be approved in advance in
* writing. By default, distribution or disclosure is not permitted.
*
* The source code may be used only by ESA CORA RDHC, ESA CORA MBAD and ESA
* CORA SAGE contractors during the activity in ESA Contract 4000121650/NL/LF,
* and only for use on the CORA RDHC hardware platform (COTS or EBB).
*
* Contact Cobham Gaisler AB, sales@gaisler.com, for licensing questions.
*/
#ifndef _GPIO_H_
#define _GPIO_H_
/*
* HDSW driver for GRGPIO
*
* The main mechanics of this driver consist in managing GRGPIO device
* open/close operations. Actual GPIO operations exported to the
* user are highly connected on how the hardware registers work. Register
* manipulation should be done with constants defined in the file
* regs/grgpio-regs.h.
*/
#include <stdint.h>
struct gpio_regs_cfg {
uint32_t addr;
/* Mask representing the implemented GPIO */
uint32_t mask;
};
/*** Device interface ***/
/* Retrieve number of GRGPIO devices registered to the driver. */
int gpio_dev_count(void);
/*
* Open a GPIO device.
*
* - All GPIO ports are configured as inputs
* - Interrupts are disabled.
* - Internal data structures are initialized.
* - Device is marked opened.
* return: device handle
*/
void *gpio_open(int dev_no);
/* d: device handle
* return: DRV_OK
*/
int gpio_close(void *d);
/** Device register access **/
/*
* d: device handle
* return: Register content before newval is written
*/
uint32_t gpio_data(void *d);
/*
* d: device handle
* set: 0 - do not write register, others - write register
* newval: value to write to register
* return: Register content before newval is written
*/
uint32_t gpio_output(void *d, int set, uint32_t newval);
uint32_t gpio_direction(void *d, int set, uint32_t newval);
uint32_t gpio_intmask(void *d, int set, uint32_t newval);
uint32_t gpio_intpol(void *d, int set, uint32_t newval);
uint32_t gpio_intedge(void *d, int set, uint32_t newval);
uint32_t gpio_iflag(void *d, int set, uint32_t newval);
uint32_t gpio_pulse(void *d, int set, uint32_t newval);
uint32_t gpio_irqmap(void *d, int i, int set, uint32_t newval);
int gpio_output_or (void *d, uint32_t mask);
int gpio_output_and(void *d, uint32_t mask);
int gpio_direction_or (void *d, uint32_t mask);
int gpio_direction_and(void *d, uint32_t mask);
int gpio_intmask_or (void *d, uint32_t mask);
int gpio_intmask_and(void *d, uint32_t mask);
#endif
/*
* This source code file is part of the CORA RDHC software.
* Copyright (C) 2018, Cobham Gaisler AB - all rights reserved.
*
* Any use or redistribution in part or in whole must be approved in advance in
* writing. By default, distribution or disclosure is not permitted.
*
* The source code may be used only by ESA CORA RDHC, ESA CORA MBAD and ESA
* CORA SAGE contractors during the activity in ESA Contract 4000121650/NL/LF,
* and only for use on the CORA RDHC hardware platform (COTS or EBB).
*
* Contact Cobham Gaisler AB, sales@gaisler.com, for licensing questions.
*/
/* GRSPW Packet driver Library helper functions */
#ifndef __GRSPW_PKT_LIB_H__
#define __GRSPW_PKT_LIB_H__
#include <bsp/grspw_pkt.h>
/* GRSPW Device handles and DMA handles */
struct grspw_dev {
void *dh;
void *dma[4];
int index;
struct grspw_hw_sup hwsup;
};
/* Driver configuration options described in memory */
struct grspw_config {
struct grspw_addr_config adrcfg;
int rmap_cfg;
unsigned char rmap_dstkey;
int tc_cfg;
void (*tc_isr_callback)(void *data, int tc);
void *tc_isr_arg;
/* Mask of which DMA Channels to enable. Most often only
* one DMA Channel is available, then set this to 1.
*
* By enabling a DMA Channel, the DMA Channels will be
* able to receive SpaceWire packets after SpaceWire buffers
* has been prepared for it, and transmitt SpaceWire packets
* when the user request transmission of a SpaceWire packet.
*/
unsigned int enable_chan_mask;
/* Per Channel Configuration */
struct grspw_dma_config chan[4];
/* SpW Interrupt configuration */
struct spwpkt_ic_config iccfg;
};
/* Statisics and diagnostics gathered by driver */
struct grspw_stats {
/* Statistics for the Core */
struct grspw_core_stats stats;
/* Per DMA channel statistics */
struct grspw_dma_stats chan[4];
};
/* Current state of configuration and link */
struct grspw_link_state {
int link_ctrl; /* Link Configuration */
unsigned char clkdiv_start; /* Clock Division during startup (not
* in state run) */
unsigned char clkdiv_run; /* Clock Division in run-state */
spw_link_state_t link_state; /* State (Error-Reset, Error-wait...) */
int port_cfg; /* Port Configuration */
int port_active; /* Currently active port */
};
/* Read the current driver configuration to memory */
void grspw_config_read(struct grspw_dev *dev, struct grspw_config *cfg);
/* Read the current link state from hardware */
void grspw_link_state_get(struct grspw_dev *dev, struct grspw_link_state *state);
/* Print the link state on the stdout */
void grspw_linkstate_print(struct grspw_link_state *ls);
/* Print hardware configuration from memory onto stdout */
void grspw_cfg_print(struct grspw_hw_sup *hw, struct grspw_config *cfg);
/* Copy current driver statistics to memory */
void grspw_stats_get(struct grspw_dev *dev, struct grspw_stats *stats);
/* Print GRSPW driver statistics from memory description onto stdout */
void grspw_stats_print(struct grspw_dev *dev, struct grspw_stats *stats);
/* Configure Core and DMA Channels, RMAP and TimeCode setup */
int grspw_cfg_set(struct grspw_dev *dev, struct grspw_config *cfg);
/* Start DMA operation on all open DMA channels */
int grspw_start(struct grspw_dev *dev);
/* Stop all DMA activity on all DMA channels */
void grspw_stop(struct grspw_dev *dev);
#endif /* __GRSPW_PKT_LIB_H__ */
/*
* This source code file is part of the CORA RDHC software.
* Copyright (C) 2018, Cobham Gaisler AB - all rights reserved.
*
* Any use or redistribution in part or in whole must be approved in advance in
* writing. By default, distribution or disclosure is not permitted.
*
* The source code may be used only by ESA CORA RDHC, ESA CORA MBAD and ESA
* CORA SAGE contractors during the activity in ESA Contract 4000121650/NL/LF,
* and only for use on the CORA RDHC hardware platform (COTS or EBB).
*
* Contact Cobham Gaisler AB, sales@gaisler.com, for licensing questions.
*/
#ifndef _OSAL_H_
#define _OSAL_H_
#include <stdint.h>
#include <osal_cfg.h>
/*
* Register interrupt handler
*
* The function in parameter handler is registered as the interrupt handler for
* the given interrupt source. The handler is called with arg as argument.
* Interrupt source is enabled in the interrupt controller.
*
* source: Interrupt number.
* handler: Pointer to software routine to execute when the interrupt triggers.
* arg: Passed as parameter to handler.
*
* return:
* - DRV_OK: Handler installed successfully.
* - DRV_INVALID_SOURCE: Invalid source parameter.
* - DRV_FAIL: Unknown failure.
*/
int osal_isr_register(int source, void (*handler) (void *), void *arg);
/*
* Unregister interrupt handler
*
* Unregister interrupt handler. The parameters source, handler and arg must
* be the same as used when the handler was registered with osal_isr_register.
* It is only allowed to unregister an interrupt which has previously been
* registered with osal_isr_register.
*
* source: Interrupt number.
* handler: Pointer to software routine previously installed.
* arg: Parameter value previously installed.
*
* return:
* - DRV_OK: Handler successfully unregistered.
* - DRV_INVALID_SOURCE: Invalid source parameter. Handler is not unregistered.
* - DRV_FAIL: Unknown failure. Handler is not unregistered.
*/
int osal_isr_unregister(int source, void (*handler) (void *), void *arg);
/*
* Atomic Load-Store Unsigned Byte
*
* Copy a byte from addr to temporary variable, then rewrite the addressed byte
* in memory with 0xff.
*
* In case atomic operation is required, the SPARC "ldstub" instruction can be
* used. Otherwise an emulating function is enough.
*
* Algorithm:
* tmp := *addr;
* *addr := 0xff;
* return tmp;
*
* addr: Address of byte to operate on.
*
* return: Value at addr before store.
*/
uint8_t osal_ldstub(uint8_t *addr);
#endif
/*
* This source code file is part of the CORA RDHC software.
* Copyright (C) 2018, Cobham Gaisler AB - all rights reserved.
*
* Any use or redistribution in part or in whole must be approved in advance in
* writing. By default, distribution or disclosure is not permitted.
*
* The source code may be used only by ESA CORA RDHC, ESA CORA MBAD and ESA
* CORA SAGE contractors during the activity in ESA Contract 4000121650/NL/LF,
* and only for use on the CORA RDHC hardware platform (COTS or EBB).
*
* Contact Cobham Gaisler AB, sales@gaisler.com, for licensing questions.
*/
#ifndef __OSAL_CFG_H_
#define __OSAL_CFG_H_
typedef int osal_int_level_t;
#define SPIN_DECLARE(name)
#define SPIN_INIT(lock, name)
#define SPIN_LOCK(lock, level)
#define SPIN_LOCK_IRQ(lock, level)
#define SPIN_UNLOCK(lock, level)
#define SPIN_UNLOCK_IRQ(lock, level)
#define SPIN_IRQFLAGS(k)
#define SPIN_ISR_IRQFLAGS(k)
#define osal_ldstub osal_bare_ldstub
static inline uint8_t osal_bare_ldstub(uint8_t *addr)
{
uint8_t prev = *addr;
*addr = 0xff;
return prev;
}
#endif
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/*
* This source code file is part of the CORA RDHC software.
* Copyright (C) 2018, Cobham Gaisler AB - all rights reserved.
*
* Any use or redistribution in part or in whole must be approved in advance in
* writing. By default, distribution or disclosure is not permitted.
*
* The source code may be used only by ESA CORA RDHC, ESA CORA MBAD and ESA
* CORA SAGE contractors during the activity in ESA Contract 4000121650/NL/LF,
* and only for use on the CORA RDHC hardware platform (COTS or EBB).
*
* Contact Cobham Gaisler AB, sales@gaisler.com, for licensing questions.
*/
#ifndef _SPI_H_
#define _SPI_H_
#include <stdint.h>
struct spi_priv;
/* Register configuration */
struct spictrl_regs_cfg {
uint32_t addr;
int interrupt;
};
/* Values for for spi_config.wordlen */
enum spi_wordlen {
SPI_WORDLEN_4, SPI_WORDLEN_5, SPI_WORDLEN_6, SPI_WORDLEN_7,
SPI_WORDLEN_8, SPI_WORDLEN_9, SPI_WORDLEN_10, SPI_WORDLEN_11,
SPI_WORDLEN_12, SPI_WORDLEN_13, SPI_WORDLEN_14, SPI_WORDLEN_15,
SPI_WORDLEN_16, SPI_WORDLEN_32, SPI_WORDLEN_NUM
};
struct spi_config {
/* SPI clock frequency, Hz */
unsigned int freq;
/* SPI mode 0, 1, 2 or 3 */
int mode;
/* Word length, according to SPI_WORDLEN_* */
enum spi_wordlen wordlen;
/* SPI controller interrupt mask */
int intmask;
/*
* Reverse data.
* 0 - Data is transmitted LSB first.
* 1 - Data is transmitted MSB first.
*/
int rev;
/*
* Synchronous TX/RX mode.
* 0 - Allow RX to overrun.
* 1 - Prevent RX from overrunning.
*/
int sync;
int loop;
};
/* Retrieve number of SPI devices registered to the driver */
int spi_dev_count(void);
/* Open an SPI device */
struct spi_priv *spi_open(int dev_no);
/* Close an SPI device */
int spi_close(struct spi_priv *d);
/* Get event register value */
uint32_t spi_get_event(struct spi_priv *d);
/* Clear bits in the event register */
void spi_clear_event(struct spi_priv *d, uint32_t event);
void spi_set_slvsel(struct spi_priv *d, uint32_t val);
/* Configure SPI device */
int spi_config(struct spi_priv *d, struct spi_config *cfg);
/* Start SPI device */
int spi_start(struct spi_priv *d);
/* Stop SPI device */
int spi_stop(struct spi_priv *d);
/* Send SPI words */
int spi_write(struct spi_priv *d, const uint32_t *txbuf, int count);
/* Receive SPI words */
int spi_read(struct spi_priv *d, uint32_t *rxbuf, int count);
int spi_qmove8(
struct spi_priv *d,
const uint8_t *out,
uint8_t *in,
int length
);
int spi_qread8(
struct spi_priv *d,
uint8_t *in,
int length
);
int spi_qwrite8(
struct spi_priv *d,
const uint8_t *out,
int length
);
int spi_qisrinit(struct spi_priv *priv);
#endif
/*
* This source code file is part of the CORA RDHC software.
* Copyright (C) 2018, Cobham Gaisler AB - all rights reserved.
*
* Any use or redistribution in part or in whole must be approved in advance in
* writing. By default, distribution or disclosure is not permitted.
*
* The source code may be used only by ESA CORA RDHC, ESA CORA MBAD and ESA
* CORA SAGE contractors during the activity in ESA Contract 4000121650/NL/LF,
* and only for use on the CORA RDHC hardware platform (COTS or EBB).
*
* Contact Cobham Gaisler AB, sales@gaisler.com, for licensing questions.
*/
/*
* Library for accessing the SPI flash Cypress S79FL256S.
*
* - Independent of SPI controller driver
* - Supported devices:
* * Cypress S79FL256S
*
* Author: Martin Åberg and Arvid Björkengren, Cobham Gaisler
*/
#ifndef SPIFLASH_H
#define SPIFLASH_H
#include <stdint.h>
enum {
SPIFLASH_OK,
SPIFLASH_FAILED,
};
enum {
SPIFLASH_WAIT_ERASE,
SPIFLASH_WAIT_PROGRAM,
SPIFLASH_WAIT_NUM,
};
struct spiflash_ctx;
struct spiflash_oparg;
/* SPI controller driver specific functions provided by user at open */
struct spiflash_ops {
void (*movedata)(
struct spiflash_oparg *arg,
const uint8_t *out,
uint8_t *in,
int length
);
void (*readdata)(
struct spiflash_oparg *arg,
uint8_t *in,
int length
);
void (*writedata)(
struct spiflash_oparg *arg,
const uint8_t *out,
int length
);
void (*select)(
struct spiflash_oparg *arg
);
void (*deselect)(
struct spiflash_oparg *arg
);
/*
* Called at wait for SPI flash status write in progress to deassert.
* This functin shall return 0 iff poll shall continue.
*/
int (*waitwrite)(
struct spiflash_oparg *arg,
int what,
int i
);
};
struct spiflash_id {
uint8_t manid;
uint16_t devid;
};
int spiflash_getid(
struct spiflash_ctx *ctx,
struct spiflash_id *id
);
struct spiflash_ctx *spiflash_open(
struct spiflash_ctx *ctx,