* objective 1: test interface for a HW/SW Simulink block, possibly having more than one of these blocks (target ARM-Artix7).
* objective 2: test run-time reconfiguration
* status: 1 HW/SW Simulink block tested. Additional block to be soon added and tested. Runtime reconfiguration also to be soon added tested. A new processor implementation added for ARM-Artix7 is being used, even if for the moment it is reusing an RTEMS/LEON ExP while the proper target RTEMS/ARM ExP is still under build and test activities (this is only temporary and very shortly will be updated).
