Commit 9bebb677 authored by Thanassis Tsiodras's avatar Thanassis Tsiodras

Point to the ZestSC1 include files, for systems that contain VHDL.

parent 56d70e33
......@@ -2211,7 +2211,7 @@ def CreateAndCompileGlue(
absDview = os.path.abspath('../D_view.aadl')
absMinicv = os.path.abspath('../' + baseDir + '/mini_cv.aadl')
if os.getenv("ZESTSC1") is not None:
vhdlIncludes = "-I ~/work/Xilinx/ZestSC1/Inc/ "
vhdlIncludes = "-I ~/tool-src/misc/ZestSC1/Inc/ "
else:
vhdlIncludes = " "
if absDview not in md5s or md5s[absDview] != md5hash(absDview) or absMinicv not in md5s or md5s[absMinicv] != md5hash(absMinicv):
......
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