Commit 6633af60 authored by Tiago Jorge's avatar Tiago Jorge
Browse files

Solve issue with missing Brave header file.

parent 387c1860
......@@ -2604,7 +2604,8 @@ def ApplyPatchForDeploymentViewNeededByOcarinaForNewEllidissTools(depl_aadlFile)
# a single Function Block is associated with an FPGA configuration ("config"), since presently the HW/FPGA's VHDL projects are auto generated per Function Block. As future work,
# the auto generated process could be adapted so different Function Blocks could "live" inside a single HW/FPGA configuration.
def BraveSynthesisAndHeaderFileGen(bNoBitfile):
if bNoBitfile == False:
if bNoBitfile == True and os.path.isfile("auto-src/bravebitfiles.h"):
return
maxBitfileSize = 1526250 # 12210000 bits / 8
bitFileOffset = 0;
btfileSize = 0;
......@@ -2635,6 +2636,7 @@ extern char globalFpgaStatus_%s[20];''' % (fBlockName));
struct config_bitfile bitfiles[] = {''');
for braveMakefile in os.popen("find . -path *VHDL-DESIGN/design/Makefile*"):
os.chdir(os.path.dirname(braveMakefile))
if bNoBitfile == False:
os.environ["NANOXPLORE_BYPASS"] = "x86_64_UBUNTU_16"
with os.popen("make") as pipe:
status = pipe.read().strip()
......
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