Commit 6633af60 authored by Tiago Jorge's avatar Tiago Jorge
Browse files

Solve issue with missing Brave header file.

parent 387c1860
......@@ -2604,14 +2604,15 @@ def ApplyPatchForDeploymentViewNeededByOcarinaForNewEllidissTools(depl_aadlFile)
# a single Function Block is associated with an FPGA configuration ("config"), since presently the HW/FPGA's VHDL projects are auto generated per Function Block. As future work,
# the auto generated process could be adapted so different Function Blocks could "live" inside a single HW/FPGA configuration.
def BraveSynthesisAndHeaderFileGen(bNoBitfile):
if bNoBitfile == False:
maxBitfileSize = 1526250 # 12210000 bits / 8
bitFileOffset = 0;
btfileSize = 0;
savedDir = os.getcwd()
isFirst = True
bitFilesHeader = open("auto-src/bravebitfiles.h", "w")
bitFilesHeader.write('''
if bNoBitfile == True and os.path.isfile("auto-src/bravebitfiles.h"):
return
maxBitfileSize = 1526250 # 12210000 bits / 8
bitFileOffset = 0;
btfileSize = 0;
savedDir = os.getcwd()
isFirst = True
bitFilesHeader = open("auto-src/bravebitfiles.h", "w")
bitFilesHeader.write('''
struct config_bitfile {
char *config;
char *global_status_var;
......@@ -2620,21 +2621,22 @@ struct config_bitfile {
};
''');
for braveMakefile in os.popen("find . -path *VHDL-DESIGN/design/Makefile*"):
os.chdir(os.path.dirname(braveMakefile))
os.chdir('../..')
fBlockName = os.path.basename(os.getcwd())[4:]
os.chdir('../../' + fBlockName)
bitFilesHeader.write('''
extern char globalFpgaStatus_%s[20];''' % (fBlockName));
os.chdir(savedDir)
for braveMakefile in os.popen("find . -path *VHDL-DESIGN/design/Makefile*"):
os.chdir(os.path.dirname(braveMakefile))
os.chdir('../..')
fBlockName = os.path.basename(os.getcwd())[4:]
os.chdir('../../' + fBlockName)
bitFilesHeader.write('''
extern char globalFpgaStatus_%s[20];''' % (fBlockName));
os.chdir(savedDir)
bitFilesHeader.write('''
''');
bitFilesHeader.write('''
bitFilesHeader.write('''
struct config_bitfile bitfiles[] = {''');
for braveMakefile in os.popen("find . -path *VHDL-DESIGN/design/Makefile*"):
os.chdir(os.path.dirname(braveMakefile))
for braveMakefile in os.popen("find . -path *VHDL-DESIGN/design/Makefile*"):
os.chdir(os.path.dirname(braveMakefile))
if bNoBitfile == False:
os.environ["NANOXPLORE_BYPASS"] = "x86_64_UBUNTU_16"
with os.popen("make") as pipe:
status = pipe.read().strip()
......@@ -2645,25 +2647,25 @@ struct config_bitfile bitfiles[] = {''');
bitFilesHeader.close()
panic('Bitfile synthesis failed in "%s"' % os.getcwd())
btfileSize = os.path.getsize('bitfile-swapped.nxb') # in bytes
os.chdir('../..')
fBlockName = os.path.basename(os.getcwd())[4:]
os.chdir('../../' + fBlockName)
with os.popen("cat mini_cv.aadl | grep -o -P '(?<=FPGA_Configurations => \").*(?=\";)'") as pipe:
configs = pipe.read().strip().split(',')
for config in configs:
if isFirst:
bitFilesHeader.write('''
os.chdir('../..')
fBlockName = os.path.basename(os.getcwd())[4:]
os.chdir('../../' + fBlockName)
with os.popen("cat mini_cv.aadl | grep -o -P '(?<=FPGA_Configurations => \").*(?=\";)'") as pipe:
configs = pipe.read().strip().split(',')
for config in configs:
if isFirst:
bitFilesHeader.write('''
"%s", globalFpgaStatus_%s, %s, %s''' % (config, fBlockName, bitFileOffset, btfileSize))
isFirst = False
else:
bitFilesHeader.write(''',
isFirst = False
else:
bitFilesHeader.write(''',
"%s", globalFpgaStatus_%s, %s, %s''' % (config, fBlockName, bitFileOffset, btfileSize))
bitFileOffset = bitFileOffset + maxBitfileSize
os.chdir(savedDir)
bitFilesHeader.write('''
};''')
bitFilesHeader.close()
bitFileOffset = bitFileOffset + maxBitfileSize
os.chdir(savedDir)
bitFilesHeader.write('''
};''')
bitFilesHeader.close()
os.chdir(savedDir)
def CallBambuForBrave(bNoBitfile):
if bNoBitfile == False:
......
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