Commit e5ec7231 authored by dbarbera's avatar dbarbera
Browse files

Verify generated module

parent 24c9bea1
...@@ -126,6 +126,8 @@ def _process(process): ...@@ -126,6 +126,8 @@ def _process(process):
for signal in process.input_signals: for signal in process.input_signals:
_generate_input_signal(signal, mapping[signal['name']]) _generate_input_signal(signal, mapping[signal['name']])
g.module.verify()
with open(g.name + '.ll', 'w') as ll_file: with open(g.name + '.ll', 'w') as ll_file:
ll_file.write(str(g.module)) ll_file.write(str(g.module))
......
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