Commit 2f118ed9 authored by Laura Alexandra Sequeira Gouveia's avatar Laura Alexandra Sequeira Gouveia
Browse files

Add TASTE IV Propeties check for FPGA configuration properties on block

templates for Zynq target
parent 1e834a40
......@@ -7,8 +7,12 @@
@@-- @_Protected_PIs_@ : Protected Provided interfaces (from pi.tmplt)
@@-- @_Unprotected_PIs_@ : Unprotected Provided interfaces (from pi.tmplt)
@@-- @_Required_@ : Required interfaces (from ri.tmplt)
project @_CAPITALIZE:Node_Name_@_Zynq_Bambu_@_LOWER:Name_@ is
@@-- @_Property_Names_@ : List of User-defined properties (names)
@@-- @_Property_Values_@ |_ Vector Tag: List of User-defined properties (values)
@@IF@@ @_LOWER:Language_@ = simulink
@@TABLE@@
@@IF@@ @_LOWER:Property_Names_@ = taste_iv_properties::fpga_configurations and not @_IS_EMPTY:LOWER:Property_Values_@
project @_CAPITALIZE:Name_@_Zynq_Bambu is
type Build_Type is ("Debug", "Release");
Build : Build_Type := external ("CFG", "Debug");
......@@ -79,6 +83,8 @@ project @_CAPITALIZE:Node_Name_@_Zynq_Bambu_@_LOWER:Name_@ is
for Excluded_Source_Files use
("ert_main.c");
@@END_IF@@
end @_CAPITALIZE:Node_Name_@_Zynq_Bambu_@_LOWER:Name_@;
end @_CAPITALIZE:Name_@_Zynq_Bambu;
@@END_IF@@
@@END_TABLE@@
@@END_IF@@
......@@ -7,6 +7,6 @@
@@-- @_Protected_PIs_@ : Protected Provided interfaces (from pi.tmplt)
@@-- @_Unprotected_PIs_@ : Unprotected Provided interfaces (from pi.tmplt)
@@-- @_Required_@ : Required interfaces (from ri.tmplt)
@@IF@@ @_LOWER:Language_@ = simulink
"@_STRIP:Unprotected_PIs_@_bambu.c",
@@END_IF@@
@@-- @_Property_Names_@ : List of User-defined properties (names)
@@-- @_Property_Values_@ |_ Vector Tag: List of User-defined properties (values)
......@@ -7,6 +7,12 @@
@@-- @_Protected_PIs_@ : Protected Provided interfaces (from pi.tmplt)
@@-- @_Unprotected_PIs_@ : Unprotected Provided interfaces (from pi.tmplt)
@@-- @_Required_@ : Required interfaces (from ri.tmplt)
@@-- @_Property_Names_@ : Required interfaces (from ri.tmplt)
@@-- @_Property_Values_@ : Required interfaces (from ri.tmplt)
@@IF@@ @_LOWER:Language_@ = simulink
@@TABLE@@
@@IF@@ @_LOWER:Property_Names_@ = taste_iv_properties::fpga_configurations and @_LOWER:Property_Values_@ /= ""
"@_STRIP:Unprotected_PIs_@_bambu.c",
@@END_IF@@
@@END_TABLE@@
@@END_IF@@
......@@ -117,9 +117,6 @@ project @_CAPITALIZE:Name_@_Zynq_RTEMS is
@@IF@@ @_LOWER:Block_Languages_@ = sdl
"../../@_LOWER:Block_Names_@/SDL/code",
"../../@_LOWER:Block_Names_@/SDL/wrappers",
@@ELSIF@@ @_LOWER:Block_Languages_@ = simulink
"../../@_LOWER:Block_Names_@/@_Block_Languages_@/src",
"../../@_LOWER:Block_Names_@/@_Block_Languages_@/wrappers",
@@ELSE@@
"../../@_LOWER:Block_Names_@/@_Block_Languages_@/src",
"../../@_LOWER:Block_Names_@/@_Block_Languages_@/wrappers",
......
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