Commit c37a4b21 authored by Jerome Legrand's avatar Jerome Legrand

taste 2.2.0

parent df89defa
-- This package models the GR-Rasta GR-CPCI-XC4V LEON Compact-PCI
-- development board by AEROFlex Gaisler.
package Boards::GR_CPCI_X4CV
public
with Processors::SPARC, Memories, Data_Sheet;
with Buses::SpaceWire, Buses::UART;
------------------
-- GR_CPCI_X4CV --
------------------
system GR_CPCI_X4CV
features
spw_core_1 : requires bus access Buses::SpaceWire::SpaceWire.impl;
spw_core_2 : requires bus access Buses::SpaceWire::SpaceWire.impl;
spw_core_3 : requires bus access Buses::SpaceWire::SpaceWire.impl;
uart_core_1 : requires bus access Buses::UART::UART.impl;
uart_core_2 : requires bus access Buses::UART::UART.impl;
uart_core_3 : requires bus access Buses::UART::UART.impl;
properties
Data_Sheet::UUID => "http://www.gaisler.com/cms/index.php?option=com_content&task=view&id=253&Itemid=156";
end GR_CPCI_X4CV;
system implementation GR_CPCI_X4CV.impl
subcomponents
LEON_Core : processor Processors::SPARC::LEON2;
SRAM : memory Memories::SRAM {Memory_size => 64 MByte;};
end GR_CPCI_X4CV.impl;
end Boards::GR_CPCI_X4CV;
-- This package models the GR-Rasta GR-XC3S-1500 LEON development
-- board by AEROFlex Gaisler.
package Boards::GR_XC3S_1500
public
with Processors::SPARC, Memories, Data_Sheet;
with Buses::Ethernet, Buses::UART;
with Deployment;
with RTEMS5_UART;
------------------
-- GR_XC3S_1500 --
------------------
-- The GR-XC3S-1500 by Gaisler is a low-cost LEON board, with two
-- UARTs, one ethernet.
system GR_XC3S_1500
features
UART_Bus_0 : requires bus access Buses::UART::UART.impl;
UART_Bus_1 : requires bus access Buses::UART::UART.impl;
Eth_Bus_0 : requires bus access Buses::Ethernet::Ethernet.impl;
end GR_XC3S_1500;
system implementation GR_XC3S_1500.impl
subcomponents
LEON_Core : processor Processors::SPARC::LEON2;
SRAM : memory Memories::SRAM {Memory_size => 64 MByte;};
-- Eth_0 : device Buses::Ethernet::Generic_Ethernet;
UART_1 : device Buses::UART::Generic_UART;
UART_2 : device Buses::UART::Generic_UART;
connections
C1 : bus access UART_Bus_0 -> UART_1.UART;
C2 : bus access UART_Bus_1 -> UART_2.UART;
-- C3 : bus access Eth_Bus_0 -> Eth_0.Eth;
end GR_XC3S_1500.impl;
system implementation GR_XC3S_1500.rtems extends GR_XC3S_1500.impl
subcomponents
LEON_Core : refined to processor
{ Deployment::Execution_Platform => LEON_RTEMS;};
UART_1 : refined to device RTEMS5_UART::RTEMS5_APBUART.impl;
UART_2 : refined to device RTEMS5_UART::RTEMS5_APBUART.impl;
end GR_XC3S_1500.rtems;
end Boards::GR_XC3S_1500;
-- This package models AFDX bus
package Buses::AFDX
public
with Buses::Ethernet;
bus AFDX extends Buses::Ethernet::Ethernet
properties
Transmission_Time => [ Fixed => 0 ms .. 10ms; PerByte => 0 ms .. 10 ms; ];
end AFDX;
end Buses::AFDX;
-- This package models ARINC 429 bus
package Buses::ARINC_429
public
with Bus_Properties;
bus ARINC_429
properties
Bus_Properties::Available_Bandwidth => (12 KBytesps, 1562 KBytesps);
end ARINC_429;
end Buses::ARINC_429;
-- This package models CAN bus
package Buses::CAN
public
with Bus_Properties;
bus CAN
properties
Bus_Properties::Available_Bandwidth =>
(20 KBytesps, 100 KBytesps, 500 KBytesps, 1 MBytesps);
end CAN;
end Buses::CAN;
-- Modeling Direct memory access buses
package buses::DMA
public
bus DMA
-- Empty, to define
end DMA;
end buses::DMA;
\ No newline at end of file
-- This package models Ethernet bus
package Buses::Ethernet
public
with Bus_Properties;
bus Ethernet
properties
Bus_Properties::Available_Bandwidth =>
(10 MBytesps, 100 MBytesps, 1 GBytesps);
end Ethernet;
bus implementation Ethernet.impl
end Ethernet.impl;
device Generic_Ethernet
features
Eth : requires bus access Ethernet.impl;
end Generic_Ethernet;
end Buses::Ethernet;
package Buses::I2C
public
with Bus_Properties;
feature group I2C_Pins
features
SCL : in out event port; -- Clock line
SDA : in out event port; -- Data line
end I2C_Pins;
bus I2C
end I2C;
bus implementation I2C.impl
properties
Bus_Properties::Bandwidth => 400_000 bitsps;
end I2C.impl;
end Buses::I2C;
-- This package models MIL1553 bus
package Buses::MIL1553
public
with Bus_Properties;
bus MIL1553
properties
Bus_Properties::Available_Bandwidth => (125 KBytesps);
end MIL1553;
end Buses::MIL1553;
package Buses::Misc
public
with Electricity_Properties;
-----------
-- TIMER --
-----------
bus TIMER_bus
end TIMER_bus;
bus implementation TIMER_bus.impl
end TIMER_bus.impl;
---------
-- PWM --
---------
bus PWM_bus
end PWM_bus;
bus implementation PWM_bus.impl
end PWM_bus.impl;
-- three_phases --
bus three_phases_bus
end three_phases_bus;
bus implementation three_phases_bus.impl
end three_phases_bus.impl;
-----------
-- Power --
-----------
-- These buses model power transmission element for electric power
-- in embedded systems.
bus power
end power;
bus implementation power.i
end power.i;
bus VBat_bus
properties
Electricity_Properties::Bus_Voltage_Range => 7.0 V .. 14.8 V;
end VBat_bus;
bus implementation VBat_bus.impl
end VBat_bus.impl;
bus V3v3_bus
properties
Electricity_Properties::Bus_Voltage_Range => 3.3 V .. 3.3 V;
end V3v3_bus;
bus implementation V3v3_bus.impl
end V3v3_bus.impl;
bus V5_bus
properties
Electricity_Properties::Bus_Voltage_Range => 5.0 V .. 5.0 V;
end V5_bus;
bus implementation V5_bus.impl
end V5_bus.impl;
bus V12_bus
properties
Electricity_Properties::Bus_Voltage_Range => 12.0 V .. 12.0 V;
end V12_bus;
bus implementation V12_bus.impl
end V12_bus.impl;
bus generic_bus
end generic_bus;
bus implementation generic_bus.impl
end generic_bus.impl;
end Buses::Misc;
-- On-Board Data Handling bus modeling package
package buses::OBDH
Public
bus OBDH
-- Empty component, to define
end OBDH;
end buses::OBDH;
\ No newline at end of file
-- This package models PCI bus
package Buses::PCI
public
with Bus_Properties;
bus PCI
properties
Bus_Properties::Available_Bandwidth =>
(133 MBytesps, -- PCI 2.2
1066 MBytesps, -- PCI-X
2133 MBytesps -- PCI-X 2.0
);
end PCI;
bus implementation PCI.impl
end PCI.impl;
end Buses::PCI;
package Buses::SpaceWire
public
with Bus_Properties;
feature group LVDS
--features
-- none;
end LVDS;
bus SpaceWire
properties
Bus_Properties::Channel_Type => Full_Duplex;
Bus_Properties::Bandwidth_Scale => 2 MBytesps .. 400 MBytesps ;
end SpaceWire;
bus implementation SpaceWire.impl
end SpaceWire.impl;
end Buses::SpaceWire;
package Buses::SPI
public
bus SPI
end SPI;
bus implementation SPI.impl
end SPI.impl;
end Buses::SPI;
-- This package models UART bus
package Buses::UART
public
with Bus_Properties;
feature group UART_Pins
features
RX : in event port;
TX : out event port;
end UART_Pins;
bus UART
properties
Bus_Properties::Available_Bandwidth =>
(9_600 Bytesps, 19_200 Bytesps, 38_400 Bytesps, 57_600 Bytesps,
115_200 Bytesps);
end UART;
bus implementation UART.impl
end UART.impl;
device Generic_UART
features
UART : requires bus access UART.impl;
end Generic_UART;
end Buses::UART;
-- This package models USB bus
package Buses::USB
public
with Bus_Properties;
bus USB
properties
Bus_Properties::Available_Bandwidth =>
(1_500 KBytesps);
end USB;
bus implementation USB.impl
end USB.impl;
end Buses::USB;
-- This package models VME bus
package Buses::VME
public
with Bus_Properties;
bus VME
properties
Bus_Properties::Available_Bandwidth =>
(40 MBytesps, -- VMEbus32, VMEbus IEEE-1014
80 MBytesps, -- VME64
160 MBytesps, -- VME64x
320 MBytesps -- VME320
);
end VME;
bus implementation VME.i
end VME.i;
end Buses::VME;
-- This package models protocols layers
package Protocols
public
-- Application protocols are modeled as AADLv2 virtual bus
-- components, and then stacked. Each protocol
----------------------
-- Generic_Protocol --
----------------------
virtual bus Generic_Protocol
end Generic_Protocol;
end Protocols;
package ASN1_Configuration
public
with Deployment;
------------------------
-- Configuration Type --
------------------------
data configuration_type_ip
properties
Type_Source_Name => "IP-Conf-T";
Deployment::ASN1_Module_Name => "POHICDRIVER-IP";
Source_Language => (ASN1);
Source_Text => ("OCARINA_INCLUDE_PATH/ocarina/runtime/polyorb-hi-c/src/drivers/configuration/ip.asn" , "drivers/configuration/ip.h");
end configuration_type_ip;
data configuration_type_serial
properties
Type_Source_Name => "Serial-Conf-T";
Deployment::ASN1_Module_Name => "POHICDRIVER-UART";
Source_Language => (ASN1);
Source_Text => ("OCARINA_INCLUDE_PATH/ocarina/runtime/polyorb-hi-c/src/drivers/configuration/serial.asn", "drivers/configuration/serial.h");
end configuration_type_serial;
data configuration_type_spacewire
properties
Type_Source_Name => "Spacewire-Conf-T";
Deployment::ASN1_Module_Name => "POHICDRIVER-SPACEWIRE";
Source_Language => (ASN1);
Source_Text => ("OCARINA_INCLUDE_PATH/ocarina/runtime/polyorb-hi-c/src/drivers/configuration/spacewire.asn", "drivers/configuration/spacewire.h");
end configuration_type_spacewire;
end ASN1_Configuration;
\ No newline at end of file
package RTEMS5_UART
public
with Deployment;
with ASN1_Configuration;
with Buses::UART;
-- This driver works for RTEMS 5 (presumably RTEMS 4.11) based on
-- drvmgr driver subsystem, using APBUART driver.
--
-- See Chapter 33 of RCC 1.3 manual
device RTEMS5_APBUART extends Buses::UART::Generic_UART
end RTEMS5_APBUART;
device implementation RTEMS5_APBUART.impl
properties
Deployment::Driver_Name => "RTEMS5_APBUART";
Device_Driver => classifier (serial_driver.impl);
Initialize_Entrypoint => classifier (spg_serial_init);
end RTEMS5_APBUART.impl;
------------
-- DRIVER --
------------
abstract serial_driver
properties
Deployment::Configuration_Type =>
classifier (ASN1_Configuration::configuration_type_serial);
Deployment::Version => "0.1beta";
Deployment::Help => "Write your ASN.1 configuration here";
end serial_driver;
abstract implementation serial_driver.impl
subcomponents
receiver_apbuart_serial : thread serial_poller.impl;
sender : subprogram spg_serial_sender;
end serial_driver.impl;
-------------
-- THREADS --
-------------
-- This thread handles the execution logic of the protocol stack.
thread serial_poller
end serial_poller;
thread implementation serial_poller.impl
calls
mycall : {
pspg : subprogram spg_serial_poller;
};
properties
Period => 1ms;
Dispatch_Protocol => Background;
end serial_poller.impl;
-----------------
-- SUBPROGRAMS --
-----------------
-- These subprograms model the high-level view of the UART protocol
-- stack. They define an API used by the stack to send and receive
-- data, and perform node's initialisation.
subprogram spg_serial_poller
-- Receive data and dispatch them to the receiving entity. This
-- program and its sibling (send) share a common protocol, not
-- defined in the AADL model.
properties
Source_Language => (C);
Source_Name => "__po_hi_c_driver_rtems_drvmgr_serial_poller";
Source_Text => ("po_hi_driver_drvmgr_common.c",
"po_hi_driver_rtems_drvmgr_serial.c");
end spg_serial_poller;
subprogram spg_serial_sender
-- Send data to a remote node. This program and its sibling
-- (receive) share a common protocol, not defined in the AADL
-- model.
properties
Source_Language => (C);
Source_Name => "__po_hi_c_driver_rtems_drvmgr_serial_sender";
Source_Text => ("po_hi_driver_drvmgr_common.c",
"po_hi_driver_rtems_drvmgr_serial.c");
end spg_serial_sender;
subprogram spg_serial_init
-- Initialize the different internal resources for managing
-- connections on a node. This subprogram has no formal visible
-- parameters, but relies on well-known data structures and
-- variables to configure the stack.
properties
Source_Language => (C);
Source_Name => "__po_hi_c_driver_rtems_drvmgr_serial_init";
Source_Text => ("po_hi_driver_drvmgr_common.c",
"po_hi_driver_rtems_drvmgr_serial.c");
end spg_serial_init;
end RTEMS5_UART;
-- This package models hierarchy of memories
package Memories
public
------------
-- EEPROM --
------------
memory EEPROM
-- properties
-- ARINC653::Access_Type => (Read, Write);
end EEPROM;
memory implementation EEPROM.impl
end EEPROM.impl;
------------------
-- Flash_Memory --
------------------
memory Flash_Memory
-- properties
-- ARINC653::Access_Type => (Read, Write);
end Flash_Memory;
memory implementation Flash_Memory.impl
end Flash_Memory.impl;
---------
-- RAM --
---------
memory RAM
-- properties
-- ARINC653::Access_Type => (Read, Write);
end RAM;
---------
-- ROM --
---------
memory ROM
-- properties
-- ARINC653::Access_Type => (Read);
end ROM;
----------
-- SRAM --
----------
memory SRAM extends RAM
end SRAM;
memory implementation SRAM.impl
end SRAM.impl;
-----------
-- NVRAM --
-----------
memory NVRAM extends RAM
end NVRAM;
memory implementation NVRAM.impl
end NVRAM.impl;
end Memories;
-- This package defines some processors from the ARM family
package Processors::ARM
public
with Data_Sheet;
with Deployment;
with Electricity_Properties;
with Processor_Properties;
with Buses::Misc;
with Buses::Ethernet;
with Buses::I2C;
with Buses::UART;
with Buses::USB;
-----------------
-- Generic_ARM --
-----------------
processor Generic_ARM
properties
Processor_Properties::Processor_Family => ARM;
Processor_Properties::Endianess => Little_Endian;
Processor_Properties::Word_Length => 32 bits;
end Generic_ARM;
-------------------
--