Keep 'somplete' signal high until 'start' is raised again, in TASTE wrapper...

Keep 'somplete' signal high until 'start' is raised again, in TASTE wrapper (Bambu internal one is a Pulse).

dmt/B_mappers/brave_B_mapper.py

@@ -947,10 +947,13 @@ g_placeholders = {
     "updateStartCompleteLedRegs": '',
     "updateStartStopPulses": '',
     "readinputdata": '',
+    "setStartSignalsLow": '',
     "outputs": '',
     "completions": '',
     "writeoutputdata": '',
-    "connectionsToSystemC": ''
+    "connectionsToSystemC": '',
+    "updateCalculationsCompleteReset": '',
+    "updateCalculationsComplete": ''
 }
 
 
@@ -1114,7 +1117,8 @@ def OnFinal() -> None:
     signal %(pi)s_StartCalculationsInternalOld : std_logic;
     signal %(pi)s_StartCalculationsInternal : std_logic;
     signal %(pi)s_StartCalculationsPulse : std_logic;
-    signal %(pi)s_CalculationsComplete : std_logic;          -- the finish signal for %(pi)s
+    signal %(pi)s_CalculationsCompletePulse : std_logic;          -- the finish signal for %(pi)s
+    signal %(pi)s_CalculationsComplete : std_logic;          -- the finish signal register
 
 ''' % {'pi': c._spCleanName})
 
@@ -1137,17 +1141,30 @@ def OnFinal() -> None:
                  '            %(pi)s_StartCalculationsInternalOld <= %(pi)s_StartCalculationsInternal;\n' % {'pi': c._spCleanName})
 
         AddToStr('readinputdata', '\n'.join([' ' * 22 + x for x in readinputdataLines]) + '\n')
+        
+        AddToStr('setStartSignalsLow', ' ' * 12 + "if(%s_CalculationsCompletePulse = '1') then\n" % c._spCleanName)
+        AddToStr('setStartSignalsLow', ' ' * 12 + "     %s_StartCalculationsInternal    <= '0';\n" % c._spCleanName)
+        AddToStr('setStartSignalsLow', ' ' * 12 + "     %s_StartCalculationsPulse       <= '0';\n" % c._spCleanName)
+        AddToStr('setStartSignalsLow', ' ' * 12 + "     %s_StartCalculationsInternalOld <= '0';\n" % c._spCleanName)
+        AddToStr('setStartSignalsLow', ' ' * 12 + "end if;\n")
+        
         AddToStr('writeoutputdata', '\n'.join([' ' * 16 + x for x in writeoutputdataLines]) + '\n')
 
         AddToStr('connectionsToSystemC', '\n    Interface_%s : bambu_%s\n' % (c._spCleanName, c._spCleanName))
         AddToStr('connectionsToSystemC', '        port map (\n')
         AddToStr('connectionsToSystemC', ',\n'.join(['            ' + x for x in connectionsToSystemCLines]) + ',\n')
         AddToStr('connectionsToSystemC', '            start_%s => %s_StartCalculationsPulse,\n' % (c._spCleanName, c._spCleanName))
-        AddToStr('connectionsToSystemC', '            finish_%s => %s_CalculationsComplete,\n' % (c._spCleanName, c._spCleanName))
+        AddToStr('connectionsToSystemC', '            finish_%s => %s_CalculationsCompletePulse,\n' % (c._spCleanName, c._spCleanName))
         AddToStr('connectionsToSystemC', '            clock_%s => clk_i,\n' % c._spCleanName)
         AddToStr('connectionsToSystemC', '            reset_%s => reset_n\n' % c._spCleanName)
         AddToStr('connectionsToSystemC', '        );\n')
 
+        AddToStr('updateCalculationsCompleteReset', ' ' * 12 + "%s_CalculationsComplete    <= '0';\n" % c._spCleanName)
+        AddToStr('updateCalculationsComplete', ' ' * 12 + "if(%s_CalculationsCompletePulse = '1') then\n" % c._spCleanName)
+        AddToStr('updateCalculationsComplete', ' ' * 12 + "    %s_CalculationsComplete <= '1';\n" % c._spCleanName)
+        AddToStr('updateCalculationsComplete', ' ' * 12 + "elsif (%s_StartCalculationsPulse='1') then\n" % c._spCleanName)
+        AddToStr('updateCalculationsComplete', ' ' * 12 + "    %s_CalculationsComplete <= '0';\n" % c._spCleanName)
+        AddToStr('updateCalculationsComplete', ' ' * 12 + "end if;\n")
 
     AddToStr('outputs', ', '.join(outputs) + (', ' if len(outputs) else ''))
     AddToStr('completions', ', '.join(completions))

dmt/B_mappers/vhdlTemplateBrave.py

@@ -96,6 +96,7 @@ begin
 %(readinputdata)s
                  end case;
             end if;
+%(setStartSignalsLow)s
         end if;
     end process;
 
@@ -115,6 +116,15 @@ begin
     -- Connections to the VHDL circuits
 %(connectionsToSystemC)s
 
+    process(reset_n, clk_i)
+    begin
+        if (reset_n='0') then
+%(updateCalculationsCompleteReset)s
+        elsif (clk_i'event and clk_i='1') then
+%(updateCalculationsComplete)s
+        end if;
+    end process;
+
 end arch;'''
 
 makefile = r'''
@@ -370,6 +380,8 @@ if not project.route():
 
 project.save('routed.nxm')
 
+project.save('routed.vhd')
+
 #reports
 project.reportInstances()
 

setup.py

@@ -11,7 +11,7 @@ from setuptools import setup, find_packages
 
 setup(
     name='dmt',
-    version="2.1.36",
+    version="2.1.37",
     packages=find_packages(),
     author='Thanassis Tsiodras',
     author_email='Thanassis.Tsiodras@esa.int',