Commit edc334fc authored by Thanassis Tsiodras's avatar Thanassis Tsiodras
Browse files

Merge branch 'CoRA' of https://gitrepos.estec.esa.int/taste/dmt into CoRA

parents 1aba3e45 9c34b707
...@@ -386,9 +386,11 @@ def ProcessCustomBackends( ...@@ -386,9 +386,11 @@ def ProcessCustomBackends(
else: else:
panic("Unexpected call of getCustomBackends...") # pragma: no cover panic("Unexpected call of getCustomBackends...") # pragma: no cover
for si in [x for x in SystemsAndImplementations if x[2] is not None and x[2].lower() in ["gui_ri", "gui_pi", "vhdl"]]: for si in [x for x in SystemsAndImplementations if x[2] is not None and x[4] is not None and (x[2].lower() in ["gui_ri", "gui_pi", "vhdl"] or (x[2].lower() == "c" and x[4] is not ''))]:
# We do, start the work # We do, start the work
spName, sp_impl, lang, maybeFVname = si[0], si[1], si[2], si[3] spName, sp_impl, lang, maybeFVname = si[0], si[1], si[2], si[3]
if si[2].lower() == "c" and si[4] is not '':
lang = "vhdl"
sp = commonPy.aadlAST.g_apLevelContainers[spName] sp = commonPy.aadlAST.g_apLevelContainers[spName]
if len(sp._params) == 0: if len(sp._params) == 0:
if lang.lower() == "gui_ri": # pragma: no cover if lang.lower() == "gui_ri": # pragma: no cover
......
...@@ -1212,9 +1212,6 @@ class Parser(antlr.LLkParser): ...@@ -1212,9 +1212,6 @@ class Parser(antlr.LLkParser):
if property._name[-15:].lower() == "source_language": if property._name[-15:].lower() == "source_language":
stripQuotes = property._propertyExpressionOrList.replace("\"", "") stripQuotes = property._propertyExpressionOrList.replace("\"", "")
sp.SetLanguage(stripQuotes) sp.SetLanguage(stripQuotes)
elif property._name[-10:].lower() == "fpga_modes":
stripQuotes = property._propertyExpressionOrList.replace("\"", "")
sp.SetFPGAModes(stripQuotes)
elif la1 and la1 in [END,ANNEX]: elif la1 and la1 in [END,ANNEX]:
pass pass
else: else:
...@@ -1254,7 +1251,7 @@ class Parser(antlr.LLkParser): ...@@ -1254,7 +1251,7 @@ class Parser(antlr.LLkParser):
if not g_apLevelContainers.has_key(typeid.getText()): if not g_apLevelContainers.has_key(typeid.getText()):
panic("Line %d: Subprogram (%s) must first be declared before it is implemented" % (typeid.getLine(), typeid.getText())) panic("Line %d: Subprogram (%s) must first be declared before it is implemented" % (typeid.getLine(), typeid.getText()))
sp = g_apLevelContainers[typeid.getText()] sp = g_apLevelContainers[typeid.getText()]
g_subProgramImplementations.append([typeid.getText(), defid.getText(), sp._language, "" ]) g_subProgramImplementations.append([typeid.getText(), defid.getText(), sp._language, "", sp._fpgaConfigurations])
la1 = self.LA(1) la1 = self.LA(1)
if False: if False:
pass pass
...@@ -1333,6 +1330,9 @@ class Parser(antlr.LLkParser): ...@@ -1333,6 +1330,9 @@ class Parser(antlr.LLkParser):
stripQuotes = assoc._value.replace("\"", "") stripQuotes = assoc._value.replace("\"", "")
#sp.SetLanguage(stripQuotes) #sp.SetLanguage(stripQuotes)
g_subProgramImplementations[-1][3] = stripQuotes g_subProgramImplementations[-1][3] = stripQuotes
if assoc._name[-19:].lower() == "fpga_configurations":
stripQuotes = assoc._value.replace("\"", "")
g_subProgramImplementations[-1][4] = stripQuotes
self.match(END) self.match(END)
id = self.LT(1) id = self.LT(1)
self.match(IDENT) self.match(IDENT)
......
...@@ -275,9 +275,6 @@ subprogram_type ...@@ -275,9 +275,6 @@ subprogram_type
if property._name[-15:].lower() == "source_language": if property._name[-15:].lower() == "source_language":
stripQuotes = property._propertyExpressionOrList.replace("\"", "") stripQuotes = property._propertyExpressionOrList.replace("\"", "")
sp.SetLanguage(stripQuotes) sp.SetLanguage(stripQuotes)
elif property._name[-10:].lower() == "fpga_modes":
stripQuotes = property._propertyExpressionOrList.replace("\"", "")
sp.SetFPGAModes(stripQuotes)
} )? } )?
( annex_subclause )? ( annex_subclause )?
END eid:IDENT SEMI END eid:IDENT SEMI
......
...@@ -151,7 +151,7 @@ class ApLevelContainer: ...@@ -151,7 +151,7 @@ class ApLevelContainer:
self._calls = [] self._calls = []
self._params = [] self._params = []
self._connections = [] self._connections = []
self._fpgaModes = '' self._fpgaConfigurations = ''
self._language = None self._language = None
def AddCalledAPLC(self, idAPLC): def AddCalledAPLC(self, idAPLC):
...@@ -170,8 +170,8 @@ class ApLevelContainer: ...@@ -170,8 +170,8 @@ class ApLevelContainer:
def SetLanguage(self, language): def SetLanguage(self, language):
self._language = language self._language = language
def SetFPGAModes(self, fpgaModes): def SetFPGAConfigurations(self, fpgaConfigurations):
self._fpgaModes = fpgaModes self._fpgaConfigurations = fpgaConfigurations
class Param: class Param:
def __init__(self, aplcID, id, signal, sourceElement): def __init__(self, aplcID, id, signal, sourceElement):
......
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