Commit d9a21833 authored by Tiago Jorge's avatar Tiago Jorge
Browse files

Add support to multiple PIs

parent bda6223c
...@@ -134,7 +134,7 @@ class VHDL_Circuit: ...@@ -134,7 +134,7 @@ class VHDL_Circuit:
self._params = [] # type: List[Tuple[Param, asnParser.Typename, AsnNode]] self._params = [] # type: List[Tuple[Param, asnParser.Typename, AsnNode]]
self._spCleanName = CleanName(sp._id) self._spCleanName = CleanName(sp._id)
self._offset = VHDL_Circuit.currentOffset self._offset = VHDL_Circuit.currentOffset
VHDL_Circuit.currentOffset += 1 # reserve one register for "start" signal VHDL_Circuit.currentOffset += 4 # reserve one register for "start" signal
self._paramOffset = {} # type: Dict[str, int] self._paramOffset = {} # type: Dict[str, int]
for p in sp._params: for p in sp._params:
self._paramOffset[p._id] = VHDL_Circuit.currentOffset self._paramOffset[p._id] = VHDL_Circuit.currentOffset
...@@ -161,7 +161,7 @@ class FromVHDLToASN1SCC(RecursiveMapperGeneric[List[int], str]): # pylint: disa ...@@ -161,7 +161,7 @@ class FromVHDLToASN1SCC(RecursiveMapperGeneric[List[int], str]): # pylint: disa
lines.append(" unsigned int i;\n") lines.append(" unsigned int i;\n")
lines.append(" asn1SccSint val = 0;\n") lines.append(" asn1SccSint val = 0;\n")
lines.append(" for(i=0; i<sizeof(asn1SccSint)/4; i++) {\n") lines.append(" for(i=0; i<sizeof(asn1SccSint)/4; i++) {\n")
lines.append(" rmap_tgt_read(apb_base_address + %s - 1 + ((i+1)*4), &tmp, 4, rmap_dst_address);\n" % hex(register)) lines.append(" rmap_tgt_read(R_RMAP_BASEADR + %s - 1 + ((i+1)*4), &tmp, 4, R_RMAP_DSTADR);\n" % hex(register))
lines.append(" tmp >>= 32; // ?\n") lines.append(" tmp >>= 32; // ?\n")
lines.append(" val |= (tmp << (32*i));\n") lines.append(" val |= (tmp << (32*i));\n")
lines.append(" }\n") lines.append(" }\n")
...@@ -287,7 +287,7 @@ class FromASN1SCCtoVHDL(RecursiveMapperGeneric[str, List[int]]): # pylint: disa ...@@ -287,7 +287,7 @@ class FromASN1SCCtoVHDL(RecursiveMapperGeneric[str, List[int]]): # pylint: disa
lines.append(" asn1SccSint val = %s;\n" % srcVar) lines.append(" asn1SccSint val = %s;\n" % srcVar)
lines.append(" for(i=0; i<sizeof(asn1SccSint)/4; i++) {\n") lines.append(" for(i=0; i<sizeof(asn1SccSint)/4; i++) {\n")
lines.append(" tmp = val & 0xFFFFFFFF;\n") lines.append(" tmp = val & 0xFFFFFFFF;\n")
lines.append(" rmap_tgt_write(apb_base_address + %s - 1 + ((i+1)*4), &tmp, 4, rmap_dst_address);\n" % hex(register)) lines.append(" rmap_tgt_write(R_RMAP_BASEADR + %s - 1 + ((i+1)*4), &tmp, 4, R_RMAP_DSTADR);\n" % hex(register))
lines.append(" val >>= 32;\n") lines.append(" val >>= 32;\n")
lines.append(" }\n") lines.append(" }\n")
lines.append("}\n") lines.append("}\n")
...@@ -488,8 +488,8 @@ uint32_t count; ...@@ -488,8 +488,8 @@ uint32_t count;
#define R_RMAP_DSTADR 0xfe #define R_RMAP_DSTADR 0xfe
#define R_RMAP_BASEADR 0x80000300 #define R_RMAP_BASEADR 0x80000300
unsigned int apb_base_address = R_RMAP_BASEADR; /* Base address on Remote. This is the address to which the data is copied. */ //unsigned int apb_base_address = R_RMAP_BASEADR; /* Base address on Remote. This is the address to which the data is copied. */
unsigned int rmap_dst_address = R_RMAP_DSTADR; /* SpW Destination address. */ //unsigned int rmap_dst_address = R_RMAP_DSTADR; /* SpW Destination address. */
''') ''')
# self.g_FVname = subProgram._id # self.g_FVname = subProgram._id
...@@ -526,7 +526,7 @@ unsigned int rmap_dst_address = R_RMAP_DSTADR; /* SpW Destination address. */ ...@@ -526,7 +526,7 @@ unsigned int rmap_dst_address = R_RMAP_DSTADR; /* SpW Destination address. */
self.C_SourceFile.write(" // Now that the parameters are passed inside the FPGA, run the processing logic\n") self.C_SourceFile.write(" // Now that the parameters are passed inside the FPGA, run the processing logic\n")
self.C_SourceFile.write(' unsigned int okstart = 1;\n') self.C_SourceFile.write(' unsigned int okstart = 1;\n')
self.C_SourceFile.write(' if (rmap_tgt_write(apb_base_address + %s, &okstart, 4, rmap_dst_address)) {\n' % self.C_SourceFile.write(' if (rmap_tgt_write(R_RMAP_BASEADR + %s, &okstart, 4, R_RMAP_DSTADR)) {\n' %
hex(int(VHDL_Circuit.lookupSP[sp._id]._offset))) hex(int(VHDL_Circuit.lookupSP[sp._id]._offset)))
self.C_SourceFile.write(' LOGERROR("Failed writing Target\\n");\n') self.C_SourceFile.write(' LOGERROR("Failed writing Target\\n");\n')
self.C_SourceFile.write(' return -1;\n') self.C_SourceFile.write(' return -1;\n')
...@@ -537,7 +537,7 @@ unsigned int rmap_dst_address = R_RMAP_DSTADR; /* SpW Destination address. */ ...@@ -537,7 +537,7 @@ unsigned int rmap_dst_address = R_RMAP_DSTADR; /* SpW Destination address. */
self.C_SourceFile.write(' while (!flag && count < RETRIES){\n') self.C_SourceFile.write(' while (!flag && count < RETRIES){\n')
self.C_SourceFile.write(" // Wait for processing logic to complete\n") self.C_SourceFile.write(" // Wait for processing logic to complete\n")
self.C_SourceFile.write(' count++;\n') self.C_SourceFile.write(' count++;\n')
self.C_SourceFile.write(' if (rmap_tgt_read(apb_base_address + %s, &flag, 4, rmap_dst_address)) {\n' % self.C_SourceFile.write(' if (rmap_tgt_read(R_RMAP_BASEADR + %s, &flag, 4, R_RMAP_DSTADR)) {\n' %
hex(int(VHDL_Circuit.lookupSP[sp._id]._offset))) hex(int(VHDL_Circuit.lookupSP[sp._id]._offset)))
self.C_SourceFile.write(' LOGERROR("Failed reading Target\\n");\n') self.C_SourceFile.write(' LOGERROR("Failed reading Target\\n");\n')
self.C_SourceFile.write(' return -1;\n') self.C_SourceFile.write(' return -1;\n')
......
...@@ -36,6 +36,7 @@ from ..commonPy.asnParser import AST_Lookup, AST_Leaftypes ...@@ -36,6 +36,7 @@ from ..commonPy.asnParser import AST_Lookup, AST_Leaftypes
TSource = TypeVar('TSource') TSource = TypeVar('TSource')
TDestin = TypeVar('TDestin') TDestin = TypeVar('TDestin')
brave_seen = {}
class SynchronousToolGlueGeneratorGeneric(Generic[TSource, TDestin]): class SynchronousToolGlueGeneratorGeneric(Generic[TSource, TDestin]):
...@@ -577,13 +578,18 @@ class SynchronousToolGlueGeneratorGeneric(Generic[TSource, TDestin]): ...@@ -577,13 +578,18 @@ class SynchronousToolGlueGeneratorGeneric(Generic[TSource, TDestin]):
dispatcherSuffix = "_Brave_Dispatch" dispatcherSuffix = "_Brave_Dispatch"
if subProgramImplementation.lower() == "c" and sp._fpgaConfigurations is not '': if subProgramImplementation.lower() == "c" and sp._fpgaConfigurations is not '':
fpgaSuffix = "_Brave_Fpga" fpgaSuffix = "_Brave_Fpga"
if maybeFVname not in brave_seen:
brave_seen[maybeFVname] = 'no_init_yet';
else:
brave_seen[maybeFVname] = 'with_init_already'
if subProgramImplementation.lower() == "c" and sp._fpgaConfigurations is not '': if subProgramImplementation.lower() == "c" and sp._fpgaConfigurations is not '':
self.C_HeaderFile.write("int Execute_%s();\n" % self.CleanNameAsADAWants(sp._id + "_" + subProgramImplementation)) self.C_HeaderFile.write("int Execute_%s();\n" % self.CleanNameAsADAWants(sp._id + "_" + subProgramImplementation))
else: else:
self.C_HeaderFile.write("void Execute_%s();\n" % self.CleanNameAsADAWants(sp._id + "_" + subProgramImplementation)) self.C_HeaderFile.write("void Execute_%s();\n" % self.CleanNameAsADAWants(sp._id + "_" + subProgramImplementation))
if maybeFVname != "": if maybeFVname != "":
self.C_HeaderFile.write("void init_%s%s();\n" % (self.CleanNameAsADAWants(maybeFVname), fpgaSuffix)) if not (subProgramImplementation.lower() == "c" and sp._fpgaConfigurations is not '' and maybeFVname in brave_seen and brave_seen[maybeFVname] is 'with_init_already'):
self.C_HeaderFile.write("void init_%s%s();\n" % (self.CleanNameAsADAWants(maybeFVname), fpgaSuffix))
if subProgramImplementation.lower() == "c" and sp._fpgaConfigurations is not '': if subProgramImplementation.lower() == "c" and sp._fpgaConfigurations is not '':
self.C_HeaderFile.write("int %s_%s%s(" % (self.CleanNameAsADAWants(maybeFVname), self.CleanNameAsADAWants(sp._id), fpgaSuffix)) self.C_HeaderFile.write("int %s_%s%s(" % (self.CleanNameAsADAWants(maybeFVname), self.CleanNameAsADAWants(sp._id), fpgaSuffix))
else: else:
...@@ -625,14 +631,17 @@ class SynchronousToolGlueGeneratorGeneric(Generic[TSource, TDestin]): ...@@ -625,14 +631,17 @@ class SynchronousToolGlueGeneratorGeneric(Generic[TSource, TDestin]):
self.C_SourceFile.write("}\n\n") self.C_SourceFile.write("}\n\n")
if maybeFVname != "": if maybeFVname != "":
self.C_SourceFile.write("void init_%s%s()\n" % (self.CleanNameAsADAWants(maybeFVname), fpgaSuffix)) if not (subProgramImplementation.lower() == "c" and sp._fpgaConfigurations is not '' and maybeFVname in brave_seen and brave_seen[maybeFVname] is 'with_init_already'):
self.C_SourceFile.write("void init_%s%s()\n" % (self.CleanNameAsADAWants(maybeFVname), fpgaSuffix))
else: # pragma: no cover else: # pragma: no cover
self.C_SourceFile.write("void %s_init()\n" % self.CleanNameAsADAWants(sp._id)) # pragma: no cover self.C_SourceFile.write("void %s_init()\n" % self.CleanNameAsADAWants(sp._id)) # pragma: no cover
self.C_SourceFile.write("{\n") if not (subProgramImplementation.lower() == "c" and sp._fpgaConfigurations is not '' and maybeFVname in brave_seen and brave_seen[maybeFVname] is 'with_init_already'):
self.InitializeBlock(modelingLanguage, asnFile, sp, subProgramImplementation, maybeFVname) self.C_SourceFile.write("{\n")
# self.C_SourceFile.write(" extern void InitializeGlue();\n") self.InitializeBlock(modelingLanguage, asnFile, sp, subProgramImplementation, maybeFVname)
# self.C_SourceFile.write(" InitializeGlue();\n") # self.C_SourceFile.write(" extern void InitializeGlue();\n")
self.C_SourceFile.write("}\n\n") # self.C_SourceFile.write(" InitializeGlue();\n")
self.C_SourceFile.write("}\n\n")
if maybeFVname != "": if maybeFVname != "":
if subProgramImplementation.lower() == "c" and sp._fpgaConfigurations is not '': if subProgramImplementation.lower() == "c" and sp._fpgaConfigurations is not '':
self.C_SourceFile.write("int %s_%s%s(" % (self.CleanNameAsADAWants(maybeFVname), self.CleanNameAsADAWants(sp._id), fpgaSuffix)) self.C_SourceFile.write("int %s_%s%s(" % (self.CleanNameAsADAWants(maybeFVname), self.CleanNameAsADAWants(sp._id), fpgaSuffix))
......
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