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Commit bda6223c authored by Tiago Jorge's avatar Tiago Jorge
Browse files

Update B mapper data types and clean.

parent bf4d4d1f
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dmt/B_mappers/brave_B_mapper.py
View file @ bda6223c
......@@ -157,17 +157,14 @@ class FromVHDLToASN1SCC(RecursiveMapperGeneric[List[int], str]): # pylint: disa
register = srcVHDL[0] + srcVHDL[1]
lines = [] # type: List[str]
lines.append("{\n")
lines.append(" asn1SccT_Int32 tmp, i;\n")
lines.append(" unsigned long long tmp;\n")
lines.append(" unsigned int i;\n")
lines.append(" asn1SccSint val = 0;\n")
lines.append(" for(i=0; i<sizeof(asn1SccSint)/4; i++) {\n")
lines.append(" rmap_tgt_read(apb_base_address + %s + (i*4), &tmp, 4, rmap_dst_address);\n" % hex(register))
lines.append(" val <<= 32; val |= tmp;\n")
lines.append(" rmap_tgt_read(apb_base_address + %s - 1 + ((i+1)*4), &tmp, 4, rmap_dst_address);\n" % hex(register))
lines.append(" tmp >>= 32; // ?\n")
lines.append(" val |= (tmp << (32*i));\n")
lines.append(" }\n")
lines.append("#if WORD_SIZE == 8\n")
lines.append(" val = __builtin_bswap64(val);\n")
lines.append("#else\n")
lines.append(" val = __builtin_bswap32(val);\n")
lines.append("#endif\n")
lines.append(" %s = val;\n" % destVar)
lines.append("}\n")
srcVHDL[0] += 8
......@@ -286,11 +283,11 @@ class FromASN1SCCtoVHDL(RecursiveMapperGeneric[str, List[int]]): # pylint: disa
register = dstVHDL[0] + dstVHDL[1]
lines = [] # type: List[str]
lines.append("{\n")
lines.append(" asn1SccT_Int32 tmp, i;\n")
lines.append(" unsigned int tmp, i;\n")
lines.append(" asn1SccSint val = %s;\n" % srcVar)
lines.append(" for(i=0; i<sizeof(asn1SccSint)/4; i++) {\n")
lines.append(" tmp = val & 0xFFFFFFFF;\n")
lines.append(" rmap_tgt_write(apb_base_address + %s + (i*4), &tmp, 4, rmap_dst_address);\n" % hex(register))
lines.append(" rmap_tgt_write(apb_base_address + %s - 1 + ((i+1)*4), &tmp, 4, rmap_dst_address);\n" % hex(register))
lines.append(" val >>= 32;\n")
lines.append(" }\n")
lines.append("}\n")
......@@ -457,7 +454,7 @@ class VHDLGlueGenerator(SynchronousToolGlueGeneratorGeneric[List[int], List[int]
#define FPGA_ERROR "error"
#define FPGA_DISABLED "disabled"
#define RETRIES 1000
#define RETRIES 10
#ifdef _WIN32
......@@ -525,11 +522,11 @@ unsigned int rmap_dst_address = R_RMAP_DSTADR; /* SpW Destination address. */
# def ExecuteBlock(self, modelingLanguage, asnFile, sp, subProgramImplementation, maybeFVname):
def ExecuteBlock(self, unused_modelingLanguage: str, unused_asnFile: str, sp: ApLevelContainer, unused_subProgramImplementation: str, maybeFVname: str) -> None:
self.C_SourceFile.write(" unsigned char flag = 0;\n\n")
self.C_SourceFile.write(" unsigned int flag = 0;\n\n")
self.C_SourceFile.write(" // Now that the parameters are passed inside the FPGA, run the processing logic\n")
self.C_SourceFile.write(' unsigned char okstart = 1;\n')
self.C_SourceFile.write(' if (rmap_tgt_write(apb_base_address + %s, &okstart, 1, rmap_dst_address)) {\n' %
self.C_SourceFile.write(' unsigned int okstart = 1;\n')
self.C_SourceFile.write(' if (rmap_tgt_write(apb_base_address + %s, &okstart, 4, rmap_dst_address)) {\n' %
hex(int(VHDL_Circuit.lookupSP[sp._id]._offset)))
self.C_SourceFile.write(' LOGERROR("Failed writing Target\\n");\n')
self.C_SourceFile.write(' return -1;\n')
......@@ -540,7 +537,7 @@ unsigned int rmap_dst_address = R_RMAP_DSTADR; /* SpW Destination address. */
self.C_SourceFile.write(' while (!flag && count < RETRIES){\n')
self.C_SourceFile.write(" // Wait for processing logic to complete\n")
self.C_SourceFile.write(' count++;\n')
self.C_SourceFile.write(' if (rmap_tgt_read(apb_base_address + %s, &flag, 1, rmap_dst_address)) {\n' %
self.C_SourceFile.write(' if (rmap_tgt_read(apb_base_address + %s, &flag, 4, rmap_dst_address)) {\n' %
hex(int(VHDL_Circuit.lookupSP[sp._id]._offset)))
self.C_SourceFile.write(' LOGERROR("Failed reading Target\\n");\n')
self.C_SourceFile.write(' return -1;\n')
......
dmt/B_mappers/synchronousTool.py
View file @ bda6223c
......@@ -579,13 +579,13 @@ class SynchronousToolGlueGeneratorGeneric(Generic[TSource, TDestin]):
fpgaSuffix = "_Brave_Fpga"
if subProgramImplementation.lower() == "c" and sp._fpgaConfigurations is not '':
self.C_HeaderFile.write("asn1SccT_Int8 Execute_%s();\n" % self.CleanNameAsADAWants(sp._id + "_" + subProgramImplementation))
self.C_HeaderFile.write("int Execute_%s();\n" % self.CleanNameAsADAWants(sp._id + "_" + subProgramImplementation))
else:
self.C_HeaderFile.write("void Execute_%s();\n" % self.CleanNameAsADAWants(sp._id + "_" + subProgramImplementation))
if maybeFVname != "":
self.C_HeaderFile.write("void init_%s%s();\n" % (self.CleanNameAsADAWants(maybeFVname), fpgaSuffix))
if subProgramImplementation.lower() == "c" and sp._fpgaConfigurations is not '':
self.C_HeaderFile.write("asn1SccT_Int8 %s_%s%s(" % (self.CleanNameAsADAWants(maybeFVname), self.CleanNameAsADAWants(sp._id), fpgaSuffix))
self.C_HeaderFile.write("int %s_%s%s(" % (self.CleanNameAsADAWants(maybeFVname), self.CleanNameAsADAWants(sp._id), fpgaSuffix))
else:
self.C_HeaderFile.write("void %s_%s%s(" % (self.CleanNameAsADAWants(maybeFVname), self.CleanNameAsADAWants(sp._id), fpgaSuffix))
else: # pragma: no cover
......@@ -603,9 +603,9 @@ class SynchronousToolGlueGeneratorGeneric(Generic[TSource, TDestin]):
# Check if Function Block will exist both as SW and HW. If yes generate dispatcher function (to delegate to SW or HW).
if subProgramImplementation.lower() == "c" and sp._fpgaConfigurations is not '':
if maybeFVname != "":
self.C_HeaderFile.write("asn1SccT_Int8 %s_%s%s(" % (self.CleanNameAsADAWants(maybeFVname), self.CleanNameAsADAWants(sp._id), dispatcherSuffix))
self.C_HeaderFile.write("int %s_%s%s(" % (self.CleanNameAsADAWants(maybeFVname), self.CleanNameAsADAWants(sp._id), dispatcherSuffix))
else: # pragma: no cover
self.C_HeaderFile.write("asn1SccT_Int8 %s%s(" % (self.CleanNameAsADAWants(sp._id), dispatcherSuffix)) # pragma: no cover
self.C_HeaderFile.write("int %s%s(" % (self.CleanNameAsADAWants(sp._id), dispatcherSuffix)) # pragma: no cover
for param in sp._params:
if param._id != sp._params[0]._id:
self.C_HeaderFile.write(', ')
......@@ -618,7 +618,7 @@ class SynchronousToolGlueGeneratorGeneric(Generic[TSource, TDestin]):
self.C_HeaderFile.write("\n#endif\n")
if subProgramImplementation.lower() == "c" and sp._fpgaConfigurations is not '':
self.C_SourceFile.write("asn1SccT_Int8 Execute_%s()\n{\n" % self.CleanNameAsADAWants(sp._id + "_" + subProgramImplementation))
self.C_SourceFile.write("int Execute_%s()\n{\n" % self.CleanNameAsADAWants(sp._id + "_" + subProgramImplementation))
else:
self.C_SourceFile.write("void Execute_%s()\n{\n" % self.CleanNameAsADAWants(sp._id + "_" + subProgramImplementation))
self.ExecuteBlock(modelingLanguage, asnFile, sp, subProgramImplementation, maybeFVname)
......@@ -635,7 +635,7 @@ class SynchronousToolGlueGeneratorGeneric(Generic[TSource, TDestin]):
self.C_SourceFile.write("}\n\n")
if maybeFVname != "":
if subProgramImplementation.lower() == "c" and sp._fpgaConfigurations is not '':
self.C_SourceFile.write("asn1SccT_Int8 %s_%s%s(" % (self.CleanNameAsADAWants(maybeFVname), self.CleanNameAsADAWants(sp._id), fpgaSuffix))
self.C_SourceFile.write("int %s_%s%s(" % (self.CleanNameAsADAWants(maybeFVname), self.CleanNameAsADAWants(sp._id), fpgaSuffix))
else:
self.C_SourceFile.write("void %s_%s%s(" % (self.CleanNameAsADAWants(maybeFVname), self.CleanNameAsADAWants(sp._id), fpgaSuffix))
else: # pragma: no cover
......@@ -704,9 +704,9 @@ class SynchronousToolGlueGeneratorGeneric(Generic[TSource, TDestin]):
# Check if Function Block will exist both as SW and HW. If yes generate dispatcher function (to delegate to SW or HW).
if subProgramImplementation.lower() == "c" and sp._fpgaConfigurations is not '':
if maybeFVname != "":
self.C_SourceFile.write("asn1SccT_Int8 %s_%s%s(" % (self.CleanNameAsADAWants(maybeFVname), self.CleanNameAsADAWants(sp._id), dispatcherSuffix))
self.C_SourceFile.write("int %s_%s%s(" % (self.CleanNameAsADAWants(maybeFVname), self.CleanNameAsADAWants(sp._id), dispatcherSuffix))
else: # pragma: no cover
self.C_SourceFile.write("asn1SccT_Int8 %s%s(" % (self.CleanNameAsADAWants(sp._id), dispatcherSuffix)) # pragma: no cover
self.C_SourceFile.write("int %s%s(" % (self.CleanNameAsADAWants(sp._id), dispatcherSuffix)) # pragma: no cover
for param in sp._params:
if param._id != sp._params[0]._id:
self.C_SourceFile.write(', ')
......
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