Commit b35a3765 authored by Laura Alexandra Sequeira Gouveia's avatar Laura Alexandra Sequeira Gouveia
Browse files

Zynq 7000: mapper updated to generate VHDL Advanced TASTE wrapper.

parent 13287df3
...@@ -12,7 +12,7 @@ vhd = '''----------------------------------------------------------------------- ...@@ -12,7 +12,7 @@ vhd = '''-----------------------------------------------------------------------
-- __/ | -- __/ |
-- |___/ -- |___/
-- --
-- Create Date: 18/09/2019 -- Create Date: 01/04/2020
-- Design Name: TASTE -- Design Name: TASTE
-- Module Name: TASTE -- Module Name: TASTE
-- Project Name: Cora-mbad-4zynq -- Project Name: Cora-mbad-4zynq
...@@ -35,33 +35,113 @@ use ieee.numeric_std.all; ...@@ -35,33 +35,113 @@ use ieee.numeric_std.all;
entity TASTE is entity TASTE is
port ( port (
--------------------------------------------------- ---------------------------------------------------
-- AXI4 LITE CORE CONTROLLER -- -- AXI4 LITE (REGISTERS) --
--------------------------------------------------- ---------------------------------------------------
-- Clock and Reset -- Clock and Reset
S_AXI_ACLK : in std_logic; S00_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic; S00_AXI_ARESETN : in std_logic;
-- Write Address Channel -- Write Address Channel
S_AXI_AWADDR : in std_logic_vector(31 downto 0); S00_AXI_AWADDR : in std_logic_vector(31 downto 0);
S_AXI_AWVALID : in std_logic; S00_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic; S00_AXI_AWREADY : out std_logic;
-- Write Data Channel -- Write Data Channel
S_AXI_WDATA : in std_logic_vector(31 downto 0); S00_AXI_WDATA : in std_logic_vector(31 downto 0);
S_AXI_WSTRB : in std_logic_vector(3 downto 0); S00_AXI_WSTRB : in std_logic_vector(3 downto 0);
S_AXI_WVALID : in std_logic; S00_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic; S00_AXI_WREADY : out std_logic;
-- Read Address Channel -- Read Address Channel
S_AXI_ARADDR : in std_logic_vector(31 downto 0); S00_AXI_ARADDR : in std_logic_vector(31 downto 0);
S_AXI_ARVALID : in std_logic; S00_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic; S00_AXI_ARREADY : out std_logic;
-- Read Data Channel -- Read Data Channel
S_AXI_RDATA : out std_logic_vector(31 downto 0); S00_AXI_RDATA : out std_logic_vector(31 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0); S00_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic; S00_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic; S00_AXI_RREADY : in std_logic;
-- Write Response Channel -- Write Response Channel
S_AXI_BRESP : out std_logic_vector(1 downto 0); S00_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic; S00_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic S00_AXI_BREADY : in std_logic;
---------------------------------------------------
-- AXI4 LITE (DDR CONTROLLER) --
---------------------------------------------------
-- Clock and Reset
M00_AXI_ACLK : in std_logic;
M00_AXI_ARESETN : in std_logic;
-- Write Address Channel
M00_AXI_AWADDR : out std_logic_vector(31 downto 0);
M00_AXI_AWVALID : out std_logic;
M00_AXI_AWREADY : in std_logic;
-- Write Data Channel
M00_AXI_WDATA : out std_logic_vector(63 downto 0);
M00_AXI_WSTRB : out std_logic_vector(7 downto 0);
M00_AXI_WVALID : out std_logic;
M00_AXI_WREADY : in std_logic;
-- Read Address Channel
M00_AXI_ARADDR : out std_logic_vector(31 downto 0);
M00_AXI_ARVALID : out std_logic;
M00_AXI_ARREADY : in std_logic;
-- Read Data Channel
M00_AXI_RDATA : in std_logic_vector(63 downto 0);
M00_AXI_RRESP : in std_logic_vector(1 downto 0);
M00_AXI_RVALID : in std_logic;
M00_AXI_RREADY : out std_logic;
-- Write Response Channel
M00_AXI_BRESP : in std_logic_vector(1 downto 0);
M00_AXI_BVALID : in std_logic;
M00_AXI_BREADY : out std_logic;
---------------------------------------------------
-- AXI4 LITE (BRAMs) --
---------------------------------------------------
-- Clock and Reset
S01_AXI_ACLK : in std_logic;
S01_AXI_ARESETN : in std_logic;
-- Write Address Channel
S01_AXI_AWADDR : in std_logic_vector(31 downto 0);
S01_AXI_AWVALID : in std_logic;
S01_AXI_AWREADY : out std_logic;
-- Write Data Channel
S01_AXI_WDATA : in std_logic_vector(31 downto 0);
S01_AXI_WSTRB : in std_logic_vector(3 downto 0);
S01_AXI_WVALID : in std_logic;
S01_AXI_WREADY : out std_logic;
-- Read Address Channel
S01_AXI_ARADDR : in std_logic_vector(31 downto 0);
S01_AXI_ARVALID : in std_logic;
S01_AXI_ARREADY : out std_logic;
-- Read Data Channel
S01_AXI_RDATA : out std_logic_vector(31 downto 0);
S01_AXI_RRESP : out std_logic_vector(1 downto 0);
S01_AXI_RVALID : out std_logic;
S01_AXI_RREADY : in std_logic;
-- Write Response Channel
S01_AXI_BRESP : out std_logic_vector(1 downto 0);
S01_AXI_BVALID : out std_logic;
S01_AXI_BREADY : in std_logic;
---------------------------------------------------
-- AXI4 STREAM SLAVE DATA SIGNALS (FIFOs) --
---------------------------------------------------
-- Clock and Reset
S00_AXIS_ACLK : in std_logic;
S00_AXIS_ARESETN : in std_logic;
-- Data Channel
S00_AXIS_TVALID : in std_logic;
S00_AXIS_TREADY : out std_logic;
S00_AXIS_TDATA : in std_logic_vector(31 downto 0);
S00_AXIS_TLAST : in std_logic;
S00_AXIS_TDEST : in std_logic_vector(4 downto 0);
---------------------------------------------------
-- AXI4 STREAM MASTER DATA SIGNALS (FIFOs) --
---------------------------------------------------
-- Clock and Reset
M00_AXIS_ACLK : in std_logic;
M00_AXIS_ARESETN : in std_logic;
-- Data Channel
M00_AXIS_TVALID : out std_logic;
M00_AXIS_TREADY : in std_logic;
M00_AXIS_TDATA : out std_logic_vector(31 downto 0);
M00_AXIS_TLAST : out std_logic;
M00_AXIS_TID : out std_logic_vector(4 downto 0)
); );
end TASTE; end TASTE;
...@@ -81,20 +161,19 @@ architecture rtl of TASTE is ...@@ -81,20 +161,19 @@ architecture rtl of TASTE is
constant EXOKAY : std_logic_vector(1 downto 0) := "01"; constant EXOKAY : std_logic_vector(1 downto 0) := "01";
constant SLVERR : std_logic_vector(1 downto 0) := "10"; constant SLVERR : std_logic_vector(1 downto 0) := "10";
constant DECERR : std_logic_vector(1 downto 0) := "11"; constant DECERR : std_logic_vector(1 downto 0) := "11";
constant S2MM_PACKET_SIZE : integer := 1024;
---------------------------------------------------- ----------------------------------------------------
-- TYPE DEFINITION -- -- TYPE DEFINITION --
---------------------------------------------------- ----------------------------------------------------
------------------------------ ------------------------------
-- AXI LITE SLAVE CTRL -- -- S00 AXI --
------------------------------ ------------------------------
-- AXI4 LITE SLAVE CONTROLLER FSM -- type S00_AXI_states is(idle, reading, r_complete, writing, wait_resp);
type AXI_SLAVE_CTRL_states is(idle, reading, r_complete, writing, wait_resp);
-- AXI4 combinational outputs record -- type S00_AXI_comb_out is record
type AXI_SLAVE_CTRL_comb_out is record
awready : std_logic; awready : std_logic;
wready : std_logic; wready : std_logic;
...@@ -107,19 +186,69 @@ architecture rtl of TASTE is ...@@ -107,19 +186,69 @@ architecture rtl of TASTE is
end record; end record;
-- AXI4 internal signals record -- -- AXI4 internal signals record --
type AXI_SLAVE_CTRL_inter is record type S00_AXI_inter is record
current_state : AXI_SLAVE_CTRL_states; axi_state : S00_AXI_states;
r_local_address : integer; r_local_address : integer;
bresp : std_logic_vector(1 downto 0); bresp : std_logic_vector(1 downto 0);
--Registers for I/O --Registers for I/O
%(inputdeclaration)s %(s00_signals_declaration)s
done : std_logic; ddr_ext_pointer_A : std_logic_vector(31 downto 0);
startInternal : std_logic;
startInternalOld : std_logic;
doneInternal : std_logic;
end record;
constant INIT_S00_AXI_COMB_OUT : S00_AXI_comb_out := (awready => '0',
wready => '0',
arready => '0',
rdata => (others => '0'),
rresp => OKAY,
rvalid => '0',
bvalid => '0'
);
constant INIT_S00_AXI_INTER : S00_AXI_inter := (axi_state => idle,
r_local_address => 0,
bresp => OKAY,
--Registers for I/O
%(s00_signals_assign)s
ddr_ext_pointer_A => (others => '0'),
startInternal => '0',
startInternalOld => '0',
doneInternal => '0'
);
------------------------------
-- S01 AXI --
------------------------------
type S01_AXI_states is(idle, reading, r_complete, writing, wait_resp);
type S01_AXI_comb_out is record
awready : std_logic;
wready : std_logic;
arready : std_logic;
rdata : std_logic_vector(31 downto 0);
rresp : std_logic_vector(1 downto 0);
rvalid : std_logic;
bvalid : std_logic;
%(s01_signals_declaration)s
end record;
-- AXI4 internal signals record --
type S01_AXI_inter is record
axi_state : S01_AXI_states;
r_local_address : integer;
bresp : std_logic_vector(1 downto 0);
end record; end record;
constant INIT_AXI_SLAVE_CTRL_comb_out : AXI_SLAVE_CTRL_comb_out := (awready => '0', constant INIT_S01_AXI_COMB_OUT : S01_AXI_comb_out := (%(s01_signals_assign)s
awready => '0',
wready => '0', wready => '0',
arready => '0', arready => '0',
rdata => (others => '0'), rdata => (others => '0'),
...@@ -128,27 +257,143 @@ architecture rtl of TASTE is ...@@ -128,27 +257,143 @@ architecture rtl of TASTE is
bvalid => '0' bvalid => '0'
); );
constant INIT_AXI_SLAVE_CTRL_inter : AXI_SLAVE_CTRL_inter := (current_state => idle, constant INIT_S01_AXI_INTER : S01_AXI_inter := (axi_state => idle,
r_local_address => 0, r_local_address => 0,
bresp => OKAY, bresp => OKAY
--Registers for I/O );
%(inputassign)s
done => '0'
);
---------------------------------------------------
-- M00 AXI --
---------------------------------------------------
type M00_AXI_states is(idle, writing, writing_finish, reading);
type M00_AXI_comb_out is record
awaddr : std_logic_vector(31 downto 0);
awvalid : std_logic;
wdata : std_logic_vector(63 downto 0);
wstrb : std_logic_vector(7 downto 0);
wvalid : std_logic;
araddr : std_logic_vector(31 downto 0);
arvalid : std_logic;
rready : std_logic;
bready : std_logic;
%(m00_signals_declaration)s
end record;
-- AXI4 internal signals record --
type M00_AXI_inter is record
axi_state : M00_AXI_states;
end record;
constant INIT_M00_AXI_COMB_OUT : M00_AXI_comb_out := (%(m00_signals_assign)s
awaddr => (others => '0'),
awvalid => '0',
wdata => (others => '0'),
wstrb => (others => '0'),
wvalid => '0',
araddr => (others => '0'),
arvalid => '0',
rready => '0',
bready => '0'
);
constant INIT_M00_AXI_INTER : M00_AXI_inter := (axi_state => idle
);
---------------------------------------------------
-- S00 AXIS --
---------------------------------------------------
type S00_AXIS_states is(idle, runing);
type S00_AXIS_comb_out is record
tready : std_logic;
%(s00s_signals_declaration)s
end record;
type S00_AXIS_inter is record
axis_state : S00_AXIS_states;
end record;
constant INIT_S00_AXIS_COMB_OUT : S00_AXIS_comb_out := (%(s00s_signals_assign)s
tready => '0'
);
constant INIT_S00_AXIS_INTER : S00_AXIS_inter := (axis_state => idle);
---------------------------------------------------
-- M00 AXIS --
---------------------------------------------------
type M00_AXIS_states is(idle, runing);
type M00_AXIS_comb_out is record
tvalid : std_logic;
tdata : std_logic_vector(31 downto 0);
tlast : std_logic;
%(m00s_signals_declaration)s
end record;
type M00_AXIS_inter is record
axis_state : M00_AXIS_states;
current_tid : std_logic_vector(4 downto 0);
data_counter : std_logic_vector(23 downto 0);
fifo_empty_vector : std_logic_vector(31 downto 0);
end record;
constant INIT_M00_AXIS_COMB_OUT : M00_AXIS_comb_out := (%(m00s_signals_assign)s
tvalid => '0',
tdata => (others => '0'),
tlast => '0'
);
constant INIT_M00_AXIS_INTER : M00_AXIS_inter := (axis_state => idle,
current_tid => (others => '0'),
data_counter => (others => '0'),
fifo_empty_vector => (others => '1')
);
------------------------------ ------------------------------
-- SIGNAL DECLARATION -- -- SIGNAL DECLARATION --
------------------------------ ------------------------------
-- Registers for I/O -- Registers for I/O
%(ioregisters)s %(ioregisters)s
-- AXI LITE SLAVE CTRL Signals --
signal AXI_SLAVE_CTRL_r : AXI_SLAVE_CTRL_inter;
signal AXI_SLAVE_CTRL_rin : AXI_SLAVE_CTRL_inter;
signal AXI_SLAVE_CTRL_r_comb_out : AXI_SLAVE_CTRL_comb_out;
signal AXI_SLAVE_CTRL_rin_comb_out : AXI_SLAVE_CTRL_comb_out;
-- AXI LITE SLAVE Registers Signals --
signal S00_AXI_r : S00_AXI_inter;
signal S00_AXI_rin : S00_AXI_inter;
signal S00_AXI_r_comb_out : S00_AXI_comb_out;
signal S00_AXI_rin_comb_out : S00_AXI_comb_out;
-- AXI LITE MASTER AXI DDR3 Signals --
signal M00_AXI_r : M00_AXI_inter;
signal M00_AXI_rin : M00_AXI_inter;
signal M00_AXI_r_comb_out : M00_AXI_comb_out;
signal M00_AXI_rin_comb_out : M00_AXI_comb_out;
-- AXI LITE SLAVE BRAM Signals --
signal S01_AXI_r : S01_AXI_inter;
signal S01_AXI_rin : S01_AXI_inter;
signal S01_AXI_r_comb_out : S01_AXI_comb_out;
signal S01_AXI_rin_comb_out : S01_AXI_comb_out;
-- AXI STREAM SLAVE FIFOs Signals --
signal S00_AXIS_r : S00_AXIS_inter;
signal S00_AXIS_rin : S00_AXIS_inter;
signal S00_AXIS_r_comb_out : S00_AXIS_comb_out;
signal S00_AXIS_rin_comb_out : S00_AXIS_comb_out;
-- AXI STREAM MASTER FIFOs Signals --
signal M00_AXIS_r : M00_AXIS_inter;
signal M00_AXIS_rin : M00_AXIS_inter;
signal M00_AXIS_r_comb_out : M00_AXIS_comb_out;
signal M00_AXIS_rin_comb_out : M00_AXIS_comb_out;
begin begin
--------------------------------------------------- ---------------------------------------------------
...@@ -157,157 +402,624 @@ begin ...@@ -157,157 +402,624 @@ begin
-- Connections to the VHDL circuits -- Connections to the VHDL circuits
%(connectionsToSystemC)s %(connectionsToSystemC)s
%(connectionsToBRAMs)s
%(connectionsToFIFOs)s
--------------------------------------------------- ---------------------------------------------------
-- PROCESS INSTANTIATION -- -- PROCESS INSTANTIATION --
--------------------------------------------------- ---------------------------------------------------
--------------------------------------------------- ------------------------------------------------------------------------------------------
-- AXI LITE SLAVE CTRL -- -- S00 AXI --
--------------------------------------------------- ------------------------------------------------------------------------------------------
-- Sequential process -- -- Sequential process --
seq_axi_slave: process(S_AXI_ACLK) seq_axi_slave: process(S00_AXI_ACLK)
begin begin
if rising_edge(S_AXI_ACLK) then if rising_edge(S00_AXI_ACLK) then
AXI_SLAVE_CTRL_r <= AXI_SLAVE_CTRL_rin; S00_AXI_r <= S00_AXI_rin;
AXI_SLAVE_CTRL_r_comb_out <= AXI_SLAVE_CTRL_rin_comb_out; S00_AXI_r_comb_out <= S00_AXI_rin_comb_out;
end if; end if;
end process; end process;
-- Combinational process -- -- Combinational process --
comb_axi_slave: process( -- internal signals -- comb_axi_slave: process(-- Bambu signals --
AXI_SLAVE_CTRL_r, AXI_SLAVE_CTRL_r_comb_out, %(s00_signals)s
-- internal signals --
S00_AXI_r, S00_AXI_r_comb_out,
-- AXI inptuts -- -- AXI inptuts --
S_AXI_ARESETN, S_AXI_AWADDR, S_AXI_AWVALID, S_AXI_WDATA, S_AXI_WSTRB, S_AXI_WVALID, S_AXI_ARADDR, S_AXI_ARVALID, S_AXI_RREADY, S_AXI_BREADY, S00_AXI_ARESETN, S00_AXI_AWADDR, S00_AXI_AWVALID, S00_AXI_WDATA, S00_AXI_WSTRB, S00_AXI_WVALID, S00_AXI_ARADDR, S00_AXI_ARVALID, S00_AXI_RREADY, S00_AXI_BREADY
-- Bambu signals --
%(outputs)s,
%(completions)s,
%(starts)s
) )
variable v : AXI_SLAVE_CTRL_inter; variable v : S00_AXI_inter;
variable v_comb_out : AXI_SLAVE_CTRL_comb_out; variable v_comb_out : S00_AXI_comb_out;
variable comb_S_AXI_AWVALID_S_AXI_ARVALID : std_logic_vector(1 downto 0); variable comb_S00_AXI_AWVALID_S00_AXI_ARVALID : std_logic_vector(1 downto 0);
variable w_local_address : integer; variable w_local_address : integer;
begin begin
----------------------------------------------------------------- -----------------------------------------------------------------
-- DEFAULT VARIABLES ASIGNATION -- -- DEFAULT VARIABLES ASIGNATION --
----------------------------------------------------------------- -----------------------------------------------------------------
v := AXI_SLAVE_CTRL_r; v := S00_AXI_r;
----------------------------------------------------------------- -----------------------------------------------------------------
-- DEFAULT COMBINATIONAL OUTPUT VARIABLES ASIGNATION -- -- DEFAULT COMBINATIONAL OUTPUT VARIABLES ASIGNATION --
----------------------------------------------------------------- -----------------------------------------------------------------
v_comb_out := INIT_AXI_SLAVE_CTRL_comb_out; v_comb_out := INIT_S00_AXI_COMB_OUT;
%(done_start_assign)s if %(starts)s = '1' then
v.doneInternal := '0';
end if;
if %(completions)s = '1' then
v.doneInternal := '1';
end if;
----------------------------------------------------------------- -----------------------------------------------------------------
-- DEFAULT INTERNAL VARIABLE ASIGNATION -- -- DEFAULT INTERNAL VARIABLE ASIGNATION --
----------------------------------------------------------------- -----------------------------------------------------------------
w_local_address := to_integer(unsigned(S_AXI_AWADDR(15 downto 0))); w_local_address := to_integer(unsigned(S00_AXI_AWADDR(15 downto 0)));
comb_S_AXI_AWVALID_S_AXI_ARVALID := S_AXI_AWVALID&S_AXI_ARVALID; comb_S00_AXI_AWVALID_S00_AXI_ARVALID := S00_AXI_AWVALID&S00_AXI_ARVALID;
-- Update start-stop pulses -- Update start-stop pulses
%(starstoppulses)s v.startInternalOld := S00_AXI_r.startInternal;
----------------------------------------------------------------- -----------------------------------------------------------------
-- AXI LITE CTRL FSM -- -- AXI LITE CTRL FSM --
----------------------------------------------------------------- -----------------------------------------------------------------
case AXI_SLAVE_CTRL_r.current_state is case S00_AXI_r.axi_state is
when idle => when idle =>
v.bresp := OKAY; v.bresp := OKAY;
case comb_S_AXI_AWVALID_S_AXI_ARVALID is case comb_S00_AXI_AWVALID_S00_AXI_ARVALID is
when "01" => when "01" =>
v.current_state := reading; v.axi_state := reading;
when "11" => when "11" =>
v.current_state := reading; v.axi_state := reading;
when "10" => when "10" =>
v.current_state := writing; v.axi_state := writing;
when others => when others =>
v.current_state := idle; v.axi_state := idle;
end case; end case;
when writing => when writing =>
v_comb_out.awready := S_AXI_AWVALID; v_comb_out.awready := S00_AXI_AWVALID;
v_comb_out.wready := S_AXI_WVALID; v_comb_out.wready := S00_AXI_WVALID;
v.bresp := AXI_SLAVE_CTRL_r.bresp; v.bresp := S00_AXI_r.bresp;
if S_AXI_WVALID = '1' then if S00_AXI_WVALID = '1' then
v.current_state := wait_resp; v.axi_state := wait_resp;
case w_local_address is case w_local_address is
%(readinputdata)s when (0) => v.startInternal := S00_AXI_r.startInternal xor '1';
%(s00_signals_writing)s
when others => null; when others => null;
end case; end case;
end if; end if;
when wait_resp => when wait_resp =>
v_comb_out.awready := S_AXI_AWVALID; v_comb_out.awready := S00_AXI_AWVALID;
v_comb_out.wready := S_AXI_WVALID; v_comb_out.wready := S00_AXI_WVALID;
v.bresp := AXI_SLAVE_CTRL_r.bresp; v.bresp := S00_AXI_r.bresp;
v_comb_out.bvalid := S_AXI_BREADY; v_comb_out.bvalid := S00_AXI_BREADY;
if S_AXI_AWVALID = '0' then if S00_AXI_AWVALID = '0' then
v.current_state := idle; v.axi_state := idle;
else else
if S_AXI_WVALID = '1' then if S00_AXI_WVALID = '1' then
case w_local_address is case w_local_address is
%(readinputdata)s when (0) => v.startInternal := S00_AXI_r.startInternal xor '1';
%(s00_signals_writing)s
when others => null; when others => null;
end case; end case;
else else
v.current_state := writing; v.axi_state := writing;
end if; end if;
end if; end if;
when reading => when reading =>
v_comb_out.arready := S_AXI_ARVALID; v_comb_out.arready := S00_AXI_ARVALID;