Commit 9f430d68 authored by Thanassis Tsiodras's avatar Thanassis Tsiodras

Add the CoRA-required field for FPGA modes.

parent f755974c
......@@ -1212,6 +1212,9 @@ class Parser(antlr.LLkParser):
if property._name[-15:].lower() == "source_language":
stripQuotes = property._propertyExpressionOrList.replace("\"", "")
sp.SetLanguage(stripQuotes)
elif property._name[-10:].lower() == "fpga_modes":
stripQuotes = property._propertyExpressionOrList.replace("\"", "")
sp.SetFPGAModes(stripQuotes)
elif la1 and la1 in [END,ANNEX]:
pass
else:
......
......@@ -275,6 +275,9 @@ subprogram_type
if property._name[-15:].lower() == "source_language":
stripQuotes = property._propertyExpressionOrList.replace("\"", "")
sp.SetLanguage(stripQuotes)
elif property._name[-10:].lower() == "fpga_modes":
stripQuotes = property._propertyExpressionOrList.replace("\"", "")
sp.SetFPGAModes(stripQuotes)
} )?
( annex_subclause )?
END eid:IDENT SEMI
......
......@@ -151,6 +151,7 @@ class ApLevelContainer:
self._calls = []
self._params = []
self._connections = []
self._fpgaModes = ''
self._language = None
def AddCalledAPLC(self, idAPLC):
......@@ -169,6 +170,8 @@ class ApLevelContainer:
def SetLanguage(self, language):
self._language = language
def SetFPGAModes(self, fpgaModes):
self._fpgaModes = fpgaModes
class Param:
def __init__(self, aplcID, id, signal, sourceElement):
......
......@@ -11,7 +11,7 @@ from setuptools import setup, find_packages
setup(
name='dmt',
version="2.1.17",
version="2.1.18",
packages=find_packages(),
author='Thanassis Tsiodras',
author_email='Thanassis.Tsiodras@esa.int',
......
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