Commit 9c986bc9 authored by Tiago Jorge's avatar Tiago Jorge
Browse files

Update Brave Bmapper and template to new design

parent 8415c9df
This diff is collapsed.
......@@ -88,7 +88,7 @@ begin
-- Update start-stop pulses
%(updateStartStopPulses)s
if (apbi.pwrite='1' and apbi.psel= '1' and apbi.penable = '1') then
case (apbi.paddr(7 downto 0)) is
case (apbi.paddr(15 downto 0)) is
-- Read data
%(readinputdata)s
end case;
......@@ -100,14 +100,14 @@ begin
process (apbi.paddr, apbi.pwrite, %(outputs)s %(completions)s)
begin
if (apbi.pwrite='0' and apbi.psel= '1') then
case (apbi.paddr(7 downto 0)) is
case (apbi.paddr(15 downto 0)) is
-- Write data
%(writeoutputdata)s
when others => apbo.prdata <= (others => '0');
when others => apbo.prdata(7 downto 0) <= (others => '0');
end case;
else
-- avoid latches
apbo.prdata <= (others => '0');
apbo.prdata(7 downto 0) <= (others => '0');
end if;
end process;
......@@ -117,32 +117,19 @@ begin
end arch;'''
makefile = r'''
SRCS=Example1.vhd %(pi)s
SRCS=TASTE.vhd %(pi)s
TARGET=TASTE.bit
all: ${TARGET}
${TARGET}: ${SRCS}
%(tab)sxst -intstyle ise -ifn TASTE.xst -ofn TASTE.syr || exit 1
%(tab)sngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -uc ZestSC1.ucf -p xc3s1000-ft256-5 TASTE.ngc TASTE.ngd || exit 1
%(tab)smap -intstyle ise -p xc3s1000-ft256-5 -cm area -ir off -pr b -c 100 -o TASTE_map.ncd TASTE.ngd TASTE.pcf || exit 1
%(tab)spar -w -intstyle ise -ol high -t 1 TASTE_map.ncd TASTE.ncd TASTE.pcf || exit 1
%(tab)strce -intstyle ise -e 3 -s 5 -n 3 -xml TASTE.twx TASTE.ncd -o TASTE.twr TASTE.pcf -ucf ZestSC1.ucf || exit 1
%(tab)sbitgen -intstyle ise -f TASTE.ut TASTE.ncd || exit 1
%(tab)snanoxpython script.py
%(tab)s@echo "========================================"
%(tab)s@echo " ${TARGET} built successfully. "
%(tab)s@echo "========================================"
clean:
%(tab)srm -f ${TARGET}
'''
prj = '''vhdl work "craft_gatelibrary.vhd"
vhdl work "ZestSC1_SRAM.vhd"
vhdl work "ZestSC1_Host.vhd"
vhdl work "ZestSC1_Interfaces.vhd"
%(circuits)s
vhdl work "TASTE.vhd"
%(tab)srm -rf logs *.nxm *.pyc *.nxb
'''
per_circuit_vhd = """
......@@ -151,11 +138,6 @@ use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
%(declaration)s
architecture arch of %(pi)s is
......@@ -206,96 +188,205 @@ begin
end arch;
"""
xise = """<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="Example1.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="ZestSC1_Host.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="ZestSC1_SRAM.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="ZestSC1_Interfaces.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="ZestSC1.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="%(pi)s.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
</files>
<properties>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc3s1000" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Enhanced Design Summary" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|TASTE|arch" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="Example1.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/TASTE" xil_pn:valueState="non-default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="ft256" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Report Type" xil_pn:value="Error Report" xil_pn:valueState="non-default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Error Report" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="iMPACT Project File" xil_pn:value="" xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="Example1" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2016-09-25T12:57:19" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="3745F6A05FDE9EEAF3D6AE162B4C5A8F" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_mapSmartGuideFileName" xil_pn:value="" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_parSmartGuideFileName" xil_pn:value="" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
script = """import os
import sys
from os import path
from nanoxmap import *
dir = os.path.dirname(os.path.realpath(__file__))
sys.path.append(dir)
#setVerbosity(0)
project = createProject(dir)
project.setVariantName('NG-MEDIUM')
project.setTopCellName('top_lib', 'rdhc_bb')
project.addFiles('leon2ft', [
'../src/leon2ft_2015.3_nomeiko/leon/amba.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/target.vhd',
'device.vhd',
'TASTE.vhd',
'%(pi)s.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/config.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/ftlib.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/ftcell.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/sparcv8.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/mmuconfig.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/iface.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/macro.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/ambacomp.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/bprom.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/multlib.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/tech_generic.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/tech_atc18.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/tech_atc25.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/tech_atc35.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/tech_fs90.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/tech_umc18.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/tech_tsmc25.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/tech_virtex.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/tech_virtex2.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/tech_proasic.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/tech_axcel.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/tech_map.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/dsu.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/dsu_mem.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/dcom_uart.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/dcom.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/rstgen.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/irqctrl.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/ioport.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/timers.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/uart.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/ahbmst.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/apbmst.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/ahbram.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/ahbarb.vhd',
'../src/leon2ft_2015.3_nomeiko/leon/mccomp.vhd'])
project.addFiles('spwrmap', [
'../src/rmap_core_v1_00_enduser_release/src/vhdl/pkg/support_pkg.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/rmap/rmap_pkg.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/dma/dma_pkg.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/pkg/tech_pkg.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/spw/spwrlink_pkg.vhd',
'../src/rmap_core_v1_00_enduser_release/extern/uodcodec_cvsrel_2_03/src/vhdl/initfsm/initfsm_counter.vhd',
'../src/rmap_core_v1_00_enduser_release/extern/uodcodec_cvsrel_2_03/src/vhdl/initfsm/initfsm_sync.vhd',
'../src/rmap_core_v1_00_enduser_release/extern/uodcodec_cvsrel_2_03/src/vhdl/initfsm/init_fsm.vhd',
'../src/rmap_core_v1_00_enduser_release/extern/uodcodec_cvsrel_2_03/src/vhdl/other/clk10gen.vhd',
'../src/rmap_core_v1_00_enduser_release/extern/uodcodec_cvsrel_2_03/src/vhdl/other/clkmux.vhd',
'../src/rmap_core_v1_00_enduser_release/extern/uodcodec_cvsrel_2_03/src/vhdl/receive/rxclock.vhd',
'../src/rmap_core_v1_00_enduser_release/extern/uodcodec_cvsrel_2_03/src/vhdl/receive/rxcredit.vhd',
'../src/rmap_core_v1_00_enduser_release/extern/uodcodec_cvsrel_2_03/src/vhdl/receive/rxdataformat.vhd',
'../src/rmap_core_v1_00_enduser_release/extern/uodcodec_cvsrel_2_03/src/vhdl/receive/rxdecode.vhd',
'../src/rmap_core_v1_00_enduser_release/extern/uodcodec_cvsrel_2_03/src/vhdl/receive/rxdiscerr.vhd',
'../src/rmap_core_v1_00_enduser_release/extern/uodcodec_cvsrel_2_03/src/vhdl/receive/rxnchar_resync_valid.vhd',
'../src/rmap_core_v1_00_enduser_release/extern/uodcodec_cvsrel_2_03/src/vhdl/receive/rxnchar_resync_ffstore_inferfpgaram.vhd',
'../src/rmap_core_v1_00_enduser_release/extern/uodcodec_cvsrel_2_03/src/vhdl/receive/rxnchar_resync_ff.vhd',
'../src/rmap_core_v1_00_enduser_release/extern/uodcodec_cvsrel_2_03/src/vhdl/receive/rxtcode_resync.vhd',
'../src/rmap_core_v1_00_enduser_release/extern/uodcodec_cvsrel_2_03/src/vhdl/transmit/txddrreg.vhd',
'../src/rmap_core_v1_00_enduser_release/extern/uodcodec_cvsrel_2_03/src/vhdl/transmit/txddrreg_noenable.vhd',
'../src/rmap_core_v1_00_enduser_release/extern/uodcodec_cvsrel_2_03/src/vhdl/transmit/txencode.vhd',
'../src/rmap_core_v1_00_enduser_release/extern/uodcodec_cvsrel_2_03/src/vhdl/transmit/txtcode_send.vhd',
'../src/rmap_core_v1_00_enduser_release/extern/uodcodec_cvsrel_2_03/src/vhdl/txclk/txclk_divider.vhd',
'../src/rmap_core_v1_00_enduser_release/extern/uodcodec_cvsrel_2_03/src/vhdl/txclk/txclk_en_gen.vhd',
'../src/rmap_core_v1_00_enduser_release/extern/uodcodec_cvsrel_2_03/src/vhdl/txclk/txclkgen.vhd',
'../src/rmap_core_v1_00_enduser_release/extern/uodcodec_cvsrel_2_03/src/vhdl/top/spwrlink.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/mem/fifo_out_valid.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/sync_fifo/sync_fifo_logic.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/sync_fifo/sync_dpfifo.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/sync_fifo/sync_memblock_fpga_memory.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/async_fifo/async_dpfifo.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/async_fifo/async_fifo_logic.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/async_fifo/async_fifo_readptr.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/async_fifo/async_fifo_writeptr.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/async_fifo/async_memblock_fpga_memory.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/spw/spwrlinkwrap.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/spw/protocol_mux.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/spw/protocol_demux.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/spw/timecode_handler.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/spw/timecode_handler.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/dma/bus_arbiter.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/dma/dma_controller.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/dma/dma_burst_fifo_in.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/dma/dma_burst_fifo_out.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/dma/bus_master.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/rmap/unpack_rmap_word.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/rmap/pack_rmap_word.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/rmap/target_command_decode.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/rmap/target_reply_encode.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/rmap/target_controller.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/rmap/target_verify_control.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/rmap/rmap_target.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/rmap/unpack_rmap_word.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/rmap/pack_rmap_word.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/rmap/ini_command_encode.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/rmap/ini_reply_decode.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/rmap/ini_trans_controller.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/rmap/ini_delete.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/rmap/rmap_initiator.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/top/rmap_kernel.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/top/verify_buffer.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl//mem/ax_table_32x4.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl//mem/ax_table_32x5.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl//mem/ax_table_32x6.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl//mem/ax_table_32x7.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl//mem/ax_table_32x8.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl//mem/pa3_table_32x4.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl//mem/pa3_table_32x5.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl//mem/pa3_table_32x6.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl//mem/pa3_table_32x7.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl//mem/pa3_table_32x8.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/mem/transaction_table.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/top/rmap_codec_ip.vhd',
'rmap_amba.vhd'])
project.addFiles('bravecomp', ['clkgen_bm.vhd'])
project.addFiles('top_lib', ['rdhc_bb.vhd'])
project.setOptions({'UseNxLibrary': 'Yes',
'MergeRegisterToPad': 'Always',
'MultiplierToDSPMapThreshold': '1',
'ManageUnconnectedOutputs': 'Ground',
'ManageUnconnectedSignals': 'Ground',
'AdderToDSPMapThreshold': '0',
'DefaultRAMMapping': 'RAM',
'MappingEffort': 'High', 'ManageAsynchronousReadPort': 'Yes',
'TimingDriven': 'Yes'})
project.addMappingDirective('getModels(.*regfile_3p.*)', 'RAM', 'RF')
#=======================================================================================================
# Assigning timing constraints
#=======================================================================================================
# Defining the clock periods
project.createClock('getClockNet(clk25)', 'clk25', 40000, 0, 20000) # Period = 40000 ps, # first rising edge at 20000 ps -- 25 MHz
project.createClock('getClockNet(txclk)', 'txclk', 20000, 0, 10000) # Period = 20000 ps, # first rising edge at 10000 ps -- 50 MHz
project.createClock('getClockNet(spw.swloop[0].spw|rmap_codec_ip_1|spwrlinkwrap_1|spwrlink_1|RX_CLK)', 'rxclk', 20000, 0, 10000) # Period = 12500 ps, # first rising edge at 6250 ps -- 50 MHz
project.setClockGroup('getClock(clk25)', 'getClock(txclk)', 'asynchronous')
project.setClockGroup('getClock(rxclk)', 'getClock(txclk)', 'asynchronous')
project.setClockGroup('getClock(clk25)', 'getClock(rxclk)', 'asynchronous')
#=======================================================================================================
if path.exists(dir + '/pads.py'):
from pads import pads
project.addPads(pads)
project.save('native.nxm')
if not project.synthesize():
sys.exit(1)
project.save('synthesized.nxm')
if not project.place():
sys.exit(1)
project.save('placed.nxm')
if not path.exists(dir + '/pads.py'):
project.savePorts('pads.py')
if not project.route():
sys.exit(1)
project.save('routed.nxm')
#reports
project.reportInstances()
#STA
analyzer = project.createAnalyzer()
analyzer.launch()
#bitstream
project.generateBitstream('bitfile.nxb')
print 'Errors: ', getErrorCount()
print 'Warnings: ', getWarningCount()
"""
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