Commit 9c34b707 authored by Tiago Jorge's avatar Tiago Jorge
Browse files

Changed word from (fpga) modes to (fpga) configurations

parent 73d8acbf
......@@ -1212,9 +1212,6 @@ class Parser(antlr.LLkParser):
if property._name[-15:].lower() == "source_language":
stripQuotes = property._propertyExpressionOrList.replace("\"", "")
sp.SetLanguage(stripQuotes)
elif property._name[-10:].lower() == "fpga_modes":
stripQuotes = property._propertyExpressionOrList.replace("\"", "")
sp.SetFPGAModes(stripQuotes)
elif la1 and la1 in [END,ANNEX]:
pass
else:
......@@ -1254,7 +1251,7 @@ class Parser(antlr.LLkParser):
if not g_apLevelContainers.has_key(typeid.getText()):
panic("Line %d: Subprogram (%s) must first be declared before it is implemented" % (typeid.getLine(), typeid.getText()))
sp = g_apLevelContainers[typeid.getText()]
g_subProgramImplementations.append([typeid.getText(), defid.getText(), sp._language, "", sp._fpgaModes])
g_subProgramImplementations.append([typeid.getText(), defid.getText(), sp._language, "", sp._fpgaConfigurations])
la1 = self.LA(1)
if False:
pass
......@@ -1333,7 +1330,7 @@ class Parser(antlr.LLkParser):
stripQuotes = assoc._value.replace("\"", "")
#sp.SetLanguage(stripQuotes)
g_subProgramImplementations[-1][3] = stripQuotes
if assoc._name[-10:].lower() == "fpga_modes":
if assoc._name[-19:].lower() == "fpga_configurations":
stripQuotes = assoc._value.replace("\"", "")
g_subProgramImplementations[-1][4] = stripQuotes
self.match(END)
......
......@@ -275,9 +275,6 @@ subprogram_type
if property._name[-15:].lower() == "source_language":
stripQuotes = property._propertyExpressionOrList.replace("\"", "")
sp.SetLanguage(stripQuotes)
elif property._name[-10:].lower() == "fpga_modes":
stripQuotes = property._propertyExpressionOrList.replace("\"", "")
sp.SetFPGAModes(stripQuotes)
} )?
( annex_subclause )?
END eid:IDENT SEMI
......
......@@ -151,7 +151,7 @@ class ApLevelContainer:
self._calls = []
self._params = []
self._connections = []
self._fpgaModes = ''
self._fpgaConfigurations = ''
self._language = None
def AddCalledAPLC(self, idAPLC):
......@@ -170,8 +170,8 @@ class ApLevelContainer:
def SetLanguage(self, language):
self._language = language
def SetFPGAModes(self, fpgaModes):
self._fpgaModes = fpgaModes
def SetFPGAConfigurations(self, fpgaConfigurations):
self._fpgaConfigurations = fpgaConfigurations
class Param:
def __init__(self, aplcID, id, signal, sourceElement):
......
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