Commit 909655e4 authored by Tiago Jorge's avatar Tiago Jorge
Browse files

Add call to Brave dispatcher from Simulink glue

parent 4adc8cc1
......@@ -446,11 +446,13 @@ class SimulinkGlueGenerator(SynchronousToolGlueGenerator):
panicWithCallStack("%s not supported (yet?)\n" % str(param._sourceElement)) # pragma: no cover
return dstSimulink
def InitializeBlock(self, unused_modelingLanguage: str, unused_asnFile: str, unused_sp: ApLevelContainer, unused_subProgramImplementation: str, unused_maybeFVname: str) -> None:
def InitializeBlock(self, unused_modelingLanguage: str, unused_asnFile: str, sp: ApLevelContainer, unused_subProgramImplementation: str, maybeFVname: str) -> None:
self.C_SourceFile.write(" static int initialized = 0;\n")
self.C_SourceFile.write(" if (!initialized) {\n")
self.C_SourceFile.write(" initialized = 1;\n")
self.C_SourceFile.write(" %s_initialize(1);\n" % self.g_FVname)
if sp._fpgaConfigurations is not '':
self.C_SourceFile.write(" init_%s_Brave_Fpga();\n" % maybeFVname)
self.C_SourceFile.write(" }\n")
def ExecuteBlock(self, unused_modelingLanguage: str, unused_asnFile: str, unused_sp: ApLevelContainer, unused_subProgramImplementation: str, unused_maybeFVname: str) -> None:
......
......@@ -673,6 +673,21 @@ class SynchronousToolGlueGeneratorGeneric(Generic[TSource, TDestin]):
self.C_SourceFile.write('void *p' + self.CleanNameAsToolWants(param._id) + ', size_t *pSize_' + self.CleanNameAsToolWants(param._id))
self.C_SourceFile.write(")\n{\n")
if sp._fpgaConfigurations is not '' and subProgramImplementation.lower() == "simulink" and modelingLanguage != "vhdl":
self.C_SourceFile.write(' // Calling Brave VHDL dispatcher function\n')
self.C_SourceFile.write(' if (0 == %s_%s%s (' % \
(self.CleanNameAsADAWants(maybeFVname),
self.CleanNameAsADAWants(sp._id),
dispatcherSuffix))
for param in sp._params:
if param._id != sp._params[0]._id:
self.C_SourceFile.write(', ')
if isinstance(param, InParam):
self.C_SourceFile.write('p' + self.CleanNameAsToolWants(param._id) + ', size_' + self.CleanNameAsToolWants(param._id))
else:
self.C_SourceFile.write('p' + self.CleanNameAsToolWants(param._id) + ', pSize_' + self.CleanNameAsToolWants(param._id))
self.C_SourceFile.write(")) return;\n")
if genHwDevDrv:
self.C_SourceFile.write(' // Check if FPGA is ready.\n')
self.C_SourceFile.write(' extern const char globalFpgaStatus_%s[];\n' % (self.CleanNameAsADAWants(maybeFVname)))
......
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