Commit 904ff7a2 authored by Tiago Jorge's avatar Tiago Jorge
Browse files

Add a clocked PROCESS that upon each cycle copies the start and done std_logic...

Add a clocked PROCESS that upon each cycle copies the start and done std_logic signals to two registers, and also assigns two LEDs from these registers.
parent 46f67a31
......@@ -946,6 +946,7 @@ g_placeholders = {
"ioregisters": '',
"startStopSignals": '',
"reset": '',
"updateStartCompleteLedRegs": '',
"updateStartStopPulses": '',
"readinputdata": '',
"outputs": '',
......@@ -1123,6 +1124,15 @@ def OnFinal() -> None:
AddToStr('reset', " --%(pi)s_inp <= (others => '0');\n" % {'pi': c._spCleanName})
AddToStr('reset', " %(pi)s_StartCalculationsPulse <= '0';\n" % {'pi': c._spCleanName})
AddToStr('reset', " %(pi)s_StartCalculationsInternalOld <= '0';\n" % {'pi': c._spCleanName})
AddToStr('updateStartCompleteLedRegs', " led_complete_reg <= %(pi)s_CalculationsComplete;\n" % {'pi': c._spCleanName})
AddToStr('updateStartCompleteLedRegs', " if %(pi)s_StartCalculationsPulse = '1' then\n" % {'pi': c._spCleanName})
AddToStr('updateStartCompleteLedRegs', " led_start_reg <= '1';\n")
AddToStr('updateStartCompleteLedRegs', " end if;\n")
AddToStr('updateStartCompleteLedRegs', " if %(pi)s_CalculationsComplete = '1' then\n" % {'pi': c._spCleanName})
AddToStr('updateStartCompleteLedRegs', " led_start_reg <= '0';\n")
AddToStr('updateStartCompleteLedRegs', " end if;\n")
AddToStr('updateStartStopPulses',
' %(pi)s_StartCalculationsPulse <= %(pi)s_StartCalculationsInternal xor %(pi)s_StartCalculationsInternalOld;\n' % {'pi': c._spCleanName})
AddToStr('updateStartStopPulses',
......
......@@ -53,7 +53,9 @@ entity TASTE is
reset_n : in std_logic; -- System RST
-- APB interface
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
apbo : out apb_slv_out_type;
led_complete : out std_logic;
led_start : out std_logic
);
end TASTE;
......@@ -67,16 +69,25 @@ architecture arch of TASTE is
-- Signals for start/finish
%(startStopSignals)s
-- Debug signals --
signal led_start_reg : std_logic;
signal led_complete_reg : std_logic;
begin
led_complete <= led_complete_reg;
led_start <= led_start_reg;
-- Implement register write
process (reset_n, clk_i)
begin
if (reset_n='0') then
-- Signals for reset
%(reset)s
led_start_reg <= '0';
led_complete_reg <= '0';
elsif (clk_i'event and clk_i='1') then
%(updateStartCompleteLedRegs)s
-- Update start-stop pulses
%(updateStartStopPulses)s
if (apbi.pwrite='1' and apbi.psel= '1' and apbi.penable = '1') then
......
......@@ -11,7 +11,7 @@ from setuptools import setup, find_packages
setup(
name='dmt',
version="2.1.35",
version="2.1.36",
packages=find_packages(),
author='Thanassis Tsiodras',
author_email='Thanassis.Tsiodras@esa.int',
......
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