Commit 7d664534 authored by Tiago Jorge's avatar Tiago Jorge
Browse files

Always generate 'bambu_' prefixed component (even if later overwritten by Bambu).

parent 3ad568f6
......@@ -1058,9 +1058,8 @@ def OnFinal() -> None:
AddToStr('circuits', ' );\n')
AddToStr('circuits', ' end component;\n\n')
'''
skeleton = []
skeleton.append(' entity %s is\n' % c._spCleanName)
skeleton.append(' entity bambu_%s is\n' % c._spCleanName)
skeleton.append(' port (\n')
skeleton.append('\n'.join([' ' + x for x in circuitLines]) + '\n')
skeleton.append(' start_%s : in std_logic;\n' % c._spCleanName)
......@@ -1068,15 +1067,14 @@ def OnFinal() -> None:
skeleton.append(' clock_%s : in std_logic;\n' % c._spCleanName)
skeleton.append(' reset_%s : in std_logic\n' % c._spCleanName)
skeleton.append(' );\n')
skeleton.append(' end %s;\n\n' % c._spCleanName)
vhdlSkeleton = open(vhdlBackend.dir + "/TASTE-VHDL-DESIGN/design/" + c._spCleanName + '.vhd', 'w')
skeleton.append(' end bambu_%s;\n\n' % c._spCleanName)
vhdlSkeleton = open(vhdlBackend.dir + "/TASTE-VHDL-DESIGN/design/bambu_" + c._spCleanName + '.vhd', 'w')
vhdlSkeleton.write(
vhdlTemplateBrave.per_circuit_vhd % {
'pi': c._spCleanName,
'declaration': ''.join(skeleton)
})
vhdlSkeleton.close()
'''
AddToStr('ioregisters', '\n'.join([' ' + x for x in ioregisterLines]) + '\n\n')
......
......@@ -127,7 +127,7 @@ use IEEE.STD_LOGIC_UNSIGNED.ALL;
%(declaration)s
architecture arch of %(pi)s is
architecture arch of bambu_%(pi)s is
-- Declare signals
signal CLK : std_logic;
......
Supports Markdown
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment