Commit 71770813 authored by Patricia Lopez Cueva's avatar Patricia Lopez Cueva
Browse files

Integration of EBB FPGA design

parent f9a81184
......@@ -176,10 +176,10 @@ class FromVHDLToASN1SCC(RecursiveMapperGeneric[List[int], str]): # pylint: disa
def MapBoolean(self, srcVHDL: List[int], destVar: str, node: AsnBool, __: AST_Leaftypes, ___: AST_Lookup) -> List[str]: # pylint: disable=invalid-sequence-index
register = srcVHDL[0] + srcVHDL[1]
lines = [] # type: List[str]
lines = [] # type: List[str]
lines.append("{\n")
lines.append(" unsigned int tmp = 0;\n")
lines.append(" rmap_tgt_read(R_RMAP_BASEADR + %s, &tmp, 4, R_RMAP_DSTADR);\n" % hex(register))
lines.append(" rmap_tgt_read(R_RMAP_BASEADR + %s, &tmp, 4, R_RMAP_DSTADR);\n" % hex(register))
lines.append(" %s = (asn1SccUint) tmp;\n" % destVar)
lines.append("}\n")
srcVHDL[0] += 4
......@@ -193,29 +193,29 @@ class FromVHDLToASN1SCC(RecursiveMapperGeneric[List[int], str]): # pylint: disa
if isSequenceVariable(node):
panicWithCallStack("OCTET STRING (in %s) must have a fixed SIZE constraint !" % node.Location()) # pragma: no cover
if node._range[-1] % 4 != 0: # TODO
panicWithCallStack("OCTET STRING (in %s) is not a multiple of 4 bytes (this is not yet supported)." % node.Location())
panicWithCallStack("OCTET STRING (in %s) is not a multiple of 4 bytes (this is not yet supported)." % node.Location())
register = srcVHDL[0] + srcVHDL[1]
lines = [] # type: List[str]
lines.append("{\n")
lines.append(" unsigned int tmp, i;\n")
lines.append(" for(i=0; i<%d; i++) {\n" % int(node._range[-1] / 4))
lines.append(" tmp = 0;\n")
lines.append(" rmap_tgt_read(R_RMAP_BASEADR + %s + (i*4), &tmp, 4, R_RMAP_DSTADR);\n" % hex(register))
lines.append(" rmap_tgt_read(R_RMAP_BASEADR + %s + (i*4), &tmp, 4, R_RMAP_DSTADR);\n" % hex(register))
lines.append(" memcpy(%s.arr + (i*4), (unsigned char*)&tmp, sizeof(unsigned int));\n" % destVar)
lines.append(" }\n")
lines.append("}\n")
srcVHDL[0] += node._range[-1]
return lines
def MapEnumerated(self, srcVHDL: List[int], destVar: str, node: AsnEnumerated, __: AST_Leaftypes, ___: AST_Lookup) -> List[str]: # pylint: disable=invalid-sequence-index
register = srcVHDL[0] + srcVHDL[1]
lines = [] # type: List[str]
lines = [] # type: List[str]
lines.append("{\n")
lines.append(" unsigned int tmp;\n")
lines.append(" rmap_tgt_read(R_RMAP_BASEADR + %s, &tmp, 4, R_RMAP_DSTADR);\n" % hex(register))
lines.append(" rmap_tgt_read(R_RMAP_BASEADR + %s, &tmp, 4, R_RMAP_DSTADR);\n" % hex(register))
lines.append(" %s = tmp;\n" % destVar)
lines.append("}\n")
srcVHDL[0] += 4
......@@ -331,7 +331,7 @@ class FromASN1SCCtoVHDL(RecursiveMapperGeneric[str, List[int]]): # pylint: disa
lines.append(" for(i=0; i<%d; i++) {\n" % int(node._range[-1] / 4))
lines.append(" tmp = 0;\n")
lines.append(" tmp = *(unsigned int*)(%s.arr + (i*4));\n" % srcVar)
lines.append(" rmap_tgt_write(R_RMAP_BASEADR + %s + (i*4), &tmp, 4, R_RMAP_DSTADR);\n" % hex(register))
lines.append(" rmap_tgt_write(R_RMAP_BASEADR + %s + (i*4), &tmp, 4, R_RMAP_DSTADR);\n" % hex(register))
lines.append(" }\n")
lines.append("}\n")
......@@ -535,7 +535,7 @@ unsigned int count;
def ExecuteBlock(self, unused_modelingLanguage: str, unused_asnFile: str, sp: ApLevelContainer, unused_subProgramImplementation: str, maybeFVname: str) -> None:
self.C_SourceFile.write(" unsigned int flag = 0;\n\n")
self.C_SourceFile.write(" // Now that the parameters are passed inside the FPGA, run the processing logic\n")
self.C_SourceFile.write(' unsigned int okstart = 1;\n')
self.C_SourceFile.write(' if (rmap_tgt_write(R_RMAP_BASEADR + %s, &okstart, 4, R_RMAP_DSTADR)) {\n' %
hex(int(VHDL_Circuit.lookupSP[sp._id]._offset)))
......@@ -707,7 +707,7 @@ class MapASN1ToVHDLreadinputdata(RecursiveMapperGeneric[List[int], str]): # pyl
if len(node._range) > 1 and node._range[0] != node._range[1]:
panicWithCallStack("VHDL OCTET STRING (in %s) must have a fixed SIZE constraint !" % node.Location()) # pragma: no cover
if node._range[-1] % 4 != 0: # TODO
panicWithCallStack("OCTET STRING (in %s) is not a multiple of 4 bytes (this is not yet supported)." % node.Location())
panicWithCallStack("OCTET STRING (in %s) is not a multiple of 4 bytes (this is not yet supported)." % node.Location())
maxlen = len(str(node._range[-1]))
lines = [] # type: List[str]
for i in range(node._range[-1]):
......@@ -781,7 +781,7 @@ class MapASN1ToVHDLwriteoutputdata(RecursiveMapperGeneric[List[int], str]): # p
if len(node._range) > 1 and node._range[0] != node._range[1]:
panicWithCallStack("VHDL OCTET STRING (in %s) must have a fixed SIZE constraint !" % node.Location()) # pragma: no cover
if node._range[-1] % 4 != 0: # TODO
panicWithCallStack("OCTET STRING (in %s) is not a multiple of 4 bytes (this is not yet supported)." % node.Location())
panicWithCallStack("OCTET STRING (in %s) is not a multiple of 4 bytes (this is not yet supported)." % node.Location())
maxlen = len(str(node._range[-1]))
lines = [] # type: List[str]
for i in range(node._range[-1]):
......@@ -944,7 +944,6 @@ g_placeholders = {
"ioregisters": '',
"startStopSignals": '',
"reset": '',
"updateStartCompleteLedRegs": '',
"updateStartStopPulses": '',
"readinputdata": '',
"setStartSignalsLow": '',
......@@ -1092,7 +1091,7 @@ def OnFinal() -> None:
AddToStr('circuits', ' reset_%s : in std_logic\n' % c._spCleanName)
AddToStr('circuits', ' );\n')
AddToStr('circuits', ' end component;\n\n')
skeleton = []
skeleton.append(' entity bambu_%s is\n' % c._spCleanName)
skeleton.append(' port (\n')
......@@ -1127,27 +1126,19 @@ def OnFinal() -> None:
AddToStr('reset', " %(pi)s_StartCalculationsPulse <= '0';\n" % {'pi': c._spCleanName})
AddToStr('reset', " %(pi)s_StartCalculationsInternalOld <= '0';\n" % {'pi': c._spCleanName})
AddToStr('updateStartCompleteLedRegs', " led_complete_reg <= %(pi)s_CalculationsComplete;\n" % {'pi': c._spCleanName})
AddToStr('updateStartCompleteLedRegs', " if %(pi)s_StartCalculationsPulse = '1' then\n" % {'pi': c._spCleanName})
AddToStr('updateStartCompleteLedRegs', " led_start_reg <= '1';\n")
AddToStr('updateStartCompleteLedRegs', " end if;\n")
AddToStr('updateStartCompleteLedRegs', " if %(pi)s_CalculationsComplete = '1' then\n" % {'pi': c._spCleanName})
AddToStr('updateStartCompleteLedRegs', " led_start_reg <= '0';\n")
AddToStr('updateStartCompleteLedRegs', " end if;\n")
AddToStr('updateStartStopPulses',
' %(pi)s_StartCalculationsPulse <= %(pi)s_StartCalculationsInternal xor %(pi)s_StartCalculationsInternalOld;\n' % {'pi': c._spCleanName})
AddToStr('updateStartStopPulses',
' %(pi)s_StartCalculationsInternalOld <= %(pi)s_StartCalculationsInternal;\n' % {'pi': c._spCleanName})
AddToStr('readinputdata', '\n'.join([' ' * 22 + x for x in readinputdataLines]) + '\n')
AddToStr('setStartSignalsLow', ' ' * 12 + "if(%s_CalculationsCompletePulse = '1') then\n" % c._spCleanName)
AddToStr('setStartSignalsLow', ' ' * 12 + " %s_StartCalculationsInternal <= '0';\n" % c._spCleanName)
AddToStr('setStartSignalsLow', ' ' * 12 + " %s_StartCalculationsPulse <= '0';\n" % c._spCleanName)
AddToStr('setStartSignalsLow', ' ' * 12 + " %s_StartCalculationsInternalOld <= '0';\n" % c._spCleanName)
AddToStr('setStartSignalsLow', ' ' * 12 + "end if;\n")
AddToStr('writeoutputdata', '\n'.join([' ' * 16 + x for x in writeoutputdataLines]) + '\n')
AddToStr('connectionsToSystemC', '\n Interface_%s : bambu_%s\n' % (c._spCleanName, c._spCleanName))
......@@ -1239,12 +1230,12 @@ def computeBambuDeclarations(node: AsnNode, asnTypename: str, prefix: str, names
return lines
elif isinstance(node, AsnOctetString):
if not node._range:
panicWithCallStack("[computeBambuDeclarations] need a SIZE constraint or else we can't generate C code (%s)!\n" % node.Location()) # pragma: no cover
panicWithCallStack("[computeBambuDeclarations] need a SIZE constraint or else we can't generate C code (%s)!\n" % node.Location()) # pragma: no cover
lines = [] # type: List[str]
maxlen = len(str(node._range[-1]))
for i in range(0, node._range[-1]):
lines.extend(["unsigned char" + " " + prefix + "_elem_%0*d" % (maxlen, i)])
return lines
return lines
else:
panicWithCallStack("[computeBambuDeclarations] Unsupported type: " + str(node.__class__))
......@@ -1306,7 +1297,7 @@ def computeBambuInputAssignmentsForSimulink(sp: ApLevelContainer, node: AsnNode,
return lines
else:
panicWithCallStack("[computeBambuInputAssignmentsForSimulink] Unsupported type: " + str(node.__class__))
def readInputsAsBambuWantsForC(param: Param, names: AST_Lookup, leafTypeDict: AST_Leaftypes):
prefixVHDL = param._id
prefixC = "IN_" + param._id
......@@ -1360,10 +1351,10 @@ def computeBambuInputAssignmentsForC(node: AsnNode, asnTypename: str, prefixC: s
maxlen = len(str(node._range[-1]))
for i in range(0, node._range[-1]):
lines.extend([prefixC + ".arr[%d] = " % i + prefixVHDL + "_elem_%0*d" % (maxlen, i)])
return lines
return lines
else:
panicWithCallStack("[computeBambuInputAssignmentsForC] Unsupported type: " + str(node.__class__))
def writeOutputsAsBambuWantsForSimulink(sp: ApLevelContainer, param: Param, names: AST_Lookup, leafTypeDict: AST_Leaftypes):
prefixVHDL = "*" + param._id
......@@ -1477,7 +1468,7 @@ def computeBambuOutputAssignmentsForC(node: AsnNode, asnTypename: str, prefixC:
maxlen = len(str(node._range[-1]))
for i in range(0, node._range[-1]):
lines.extend([prefixVHDL + "_elem_%0*d = " % (maxlen, i) + prefixC + ".arr[%d]" % i])
return lines
return lines
else:
panicWithCallStack("[computeBambuOutputAssignmentsForC] Unsupported type: " + str(node.__class__))
......@@ -1487,9 +1478,9 @@ def EmitBambuSimulinkBridge(sp: ApLevelContainer, subProgramImplementation: str)
leafTypeDict = asnParser.g_leafTypeDict
outputCsourceFilename = vhdlBackend.CleanNameAsToolWants(sp._id) + "_bambu.c"
bambuFile = open(os.path.dirname(vhdlBackend.C_SourceFile.name) + '/' + outputCsourceFilename, 'w')
bambuFile.write("#include \"%s.h\" // Space certified compiler generated\n" % vhdlBackend.asn_name)
bambuFile.write("#include \"%s.h\"\n" % vhdlBackend.CleanNameAsToolWants(sp._id))
bambuFile.write("#include \"%s_types.h\"\n\n" % vhdlBackend.CleanNameAsToolWants(sp._id))
......@@ -1506,7 +1497,7 @@ def EmitBambuSimulinkBridge(sp: ApLevelContainer, subProgramImplementation: str)
bambuFile.write(
'%s%s' % (",\n " if idx != 0 else "", line))
bambuFile.write(') {\n')
initStr = """
static int initialized = 0;
......@@ -1525,7 +1516,7 @@ def EmitBambuSimulinkBridge(sp: ApLevelContainer, subProgramImplementation: str)
for idx, line in enumerate(lines):
bambuFile.write(
'%s%s;' % ("\n ", line))
stepStr = """
#ifndef rtmGetStopRequested
......@@ -1538,7 +1529,7 @@ def EmitBambuSimulinkBridge(sp: ApLevelContainer, subProgramImplementation: str)
#endif
""" % (sp._id, sp._id, sp._id, sp._id, sp._id)
bambuFile.write(stepStr)
lines = []
for param in sp._params:
if isinstance(param, OutParam):
......@@ -1546,8 +1537,8 @@ def EmitBambuSimulinkBridge(sp: ApLevelContainer, subProgramImplementation: str)
writeOutputsAsBambuWantsForSimulink(sp, param, names, leafTypeDict))
for idx, line in enumerate(lines):
bambuFile.write(
'%s%s;' % ("\n ", line))
'%s%s;' % ("\n ", line))
bambuFile.write('\n}\n\n')
......@@ -1557,13 +1548,13 @@ def EmitBambuCBridge(sp: ApLevelContainer, subProgramImplementation: str):
leafTypeDict = asnParser.g_leafTypeDict
outputCsourceFilename = vhdlBackend.CleanNameAsToolWants(sp._id) + "_bambu.c"
bambuFile = open(os.path.dirname(vhdlBackend.C_SourceFile.name) + '/' + outputCsourceFilename, 'w')
functionBlocksName = os.path.dirname(vhdlBackend.C_SourceFile.name)[4:] # not elegant but not sure how to get the Function Block's name from here
bambuFile.write("#include \"%s.h\" // Space certified compiler generated\n" % vhdlBackend.asn_name)
bambuFile.write("#include \"%s.h\"\n" % functionBlocksName)
bambuFile.write("#include \"%s.h\"\n" % functionBlocksName)
bambuFile.write('\nvoid bambu_%s(\n ' % sp._id)
# List flattened PI parameters
lines = []
......@@ -1574,7 +1565,7 @@ def EmitBambuCBridge(sp: ApLevelContainer, subProgramImplementation: str):
bambuFile.write(
'%s%s' % (",\n " if idx != 0 else "", line))
bambuFile.write(') {\n')
# Declare PI params
lines = []
for param in sp._params:
......@@ -1619,6 +1610,6 @@ def EmitBambuCBridge(sp: ApLevelContainer, subProgramImplementation: str):
writeOutputsAsBambuWantsForC(param, names, leafTypeDict))
for idx, line in enumerate(lines):
bambuFile.write(
'%s%s;' % ("\n ", line))
'%s%s;' % ("\n ", line))
bambuFile.write('\n}\n\n')
......@@ -53,9 +53,7 @@ entity TASTE is
reset_n : in std_logic; -- System RST
-- APB interface
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
led_complete : out std_logic;
led_start : out std_logic
apbo : out apb_slv_out_type
);
end TASTE;
......@@ -69,25 +67,16 @@ architecture arch of TASTE is
-- Signals for start/finish
%(startStopSignals)s
-- Debug signals --
signal led_start_reg : std_logic;
signal led_complete_reg : std_logic;
begin
led_complete <= led_complete_reg;
led_start <= led_start_reg;
-- Implement register write
process (reset_n, clk_i)
begin
if (reset_n='0') then
-- Signals for reset
%(reset)s
led_start_reg <= '0';
led_complete_reg <= '0';
elsif (clk_i'event and clk_i='1') then
%(updateStartCompleteLedRegs)s
-- Update start-stop pulses
%(updateStartStopPulses)s
if (apbi.pwrite='1' and apbi.psel= '1' and apbi.penable = '1') then
......@@ -209,7 +198,7 @@ project = createProject(dir)
project.setVariantName('NG-MEDIUM')
project.setTopCellName('top_lib', 'rdhc_bb')
project.setTopCellName('top_lib', 'rdhc_ebb')
project.addFiles('leon2ft', [
'../src/leon2ft_2015.3_nomeiko/leon/amba.vhd',
......@@ -328,10 +317,11 @@ project.addFiles('spwrmap', [
'../src/rmap_core_v1_00_enduser_release/src/vhdl//mem/pa3_table_32x8.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/mem/transaction_table.vhd',
'../src/rmap_core_v1_00_enduser_release/src/vhdl/top/rmap_codec_ip.vhd',
'rmap_amba.vhd'])
'../src/misc/rmap_amba.vhd'])
project.addFiles('bravecomp', ['clkgen_bm.vhd'])
project.addFiles('top_lib', ['rdhc_bb.vhd'])
project.addFiles('bravecomp', ['../src/misc/clkgen_bm.vhd'])
project.addFiles('bravecomp', ['../src/misc/pads_bm.vhd'])
project.addFiles('top_lib', ['rdhc_ebb.vhd'])
project.setOptions({'UseNxLibrary': 'Yes',
'MergeRegisterToPad': 'Always',
......@@ -346,14 +336,19 @@ project.addMappingDirective('getModels(.*regfile_3p.*)', 'RAM', 'RF')
# Defining the clock periods
project.createClock('getClockNet(clk25)', 'clk25', 40000, 0, 20000) # Period = 40000 ps, # first rising edge at 20000 ps -- 25 MHz
project.createClock('getClockNet(txclk)', 'txclk', 20000, 0, 10000) # Period = 20000 ps, # first rising edge at 10000 ps -- 50 MHz
project.createClock('getClockNet(spw.swloop[0].spw|rmap_codec_ip_1|spwrlinkwrap_1|spwrlink_1|RX_CLK)', 'rxclk', 20000, 0, 10000) # Period = 20000 ps, # first rising edge at 10000 ps -- 50 MHz
project.createClock('getClockNet(spw.swloop[0].spw|rmap_codec_ip_1|spwrlinkwrap_1|spwrlink_1|RX_CLK)', 'rxclk0', 20000, 0, 10000)
project.createClock('getClockNet(spw.swloop[1].spw|rmap_codec_ip_1|spwrlinkwrap_1|spwrlink_1|RX_CLK)', 'rxclk1', 20000, 0, 10000)
project.setClockGroup('getClock(clk25)', 'getClock(txclk)', 'asynchronous')
project.setClockGroup('getClock(txclk)', 'getClock(clk25)', 'asynchronous')
project.setClockGroup('getClock(rxclk)', 'getClock(txclk)', 'asynchronous')
project.setClockGroup('getClock(txclk)', 'getClock(rxclk)', 'asynchronous')
project.setClockGroup('getClock(clk25)', 'getClock(rxclk)', 'asynchronous')
project.setClockGroup('getClock(rxclk)', 'getClock(clk25)', 'asynchronous')
project.setClockGroup('getClock(rxclk0)', 'getClock(txclk)', 'asynchronous')
project.setClockGroup('getClock(txclk)', 'getClock(rxclk0)', 'asynchronous')
project.setClockGroup('getClock(clk25)', 'getClock(rxclk0)', 'asynchronous')
project.setClockGroup('getClock(rxclk0)', 'getClock(clk25)', 'asynchronous')
project.setClockGroup('getClock(rxclk1)', 'getClock(txclk)', 'asynchronous')
project.setClockGroup('getClock(txclk)', 'getClock(rxclk1)', 'asynchronous')
project.setClockGroup('getClock(clk25)', 'getClock(rxclk1)', 'asynchronous')
project.setClockGroup('getClock(rxclk1)', 'getClock(clk25)', 'asynchronous')
#=======================================================================================================
if path.exists(dir + '/pads.py'):
......
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