Update in NX options: 'MappingEffort': 'Low', 'ManageAsynchronousReadPort':...

Update in NX options: 'MappingEffort': 'Low', 'ManageAsynchronousReadPort': 'No', 'TimingDriven': 'Yes'

dmt/B_mappers/vhdlTemplateBrave.py

@@ -319,8 +319,8 @@ project.setOptions({'UseNxLibrary': 'Yes',
                     'ManageUnconnectedSignals': 'Ground',
                     'AdderToDSPMapThreshold': '0',
                     'DefaultRAMMapping': 'RAM',
-                    'MappingEffort': 'High', 'ManageAsynchronousReadPort': 'Yes',
-		    'TimingDriven': 'No'})
+                    'MappingEffort': 'Low', 'ManageAsynchronousReadPort': 'No',
+		    'TimingDriven': 'Yes'})
 project.addMappingDirective('getModels(.*regfile_3p.*)', 'RAM', 'RF')
 #=======================================================================================================
 # Assigning timing constraints

setup.py

@@ -11,7 +11,7 @@ from setuptools import setup, find_packages
 
 setup(
     name='dmt',
-    version="2.1.28",
+    version="2.1.29",
     packages=find_packages(),
     author='Thanassis Tsiodras',
     author_email='Thanassis.Tsiodras@esa.int',