Commit 57b6a5c2 authored by Tiago Jorge's avatar Tiago Jorge
Browse files

Fix multidefinition error conflict with vm_if by adding suffix to generated FPGA device driver

parent 1f239917
...@@ -570,10 +570,15 @@ class SynchronousToolGlueGeneratorGeneric(Generic[TSource, TDestin]): ...@@ -570,10 +570,15 @@ class SynchronousToolGlueGeneratorGeneric(Generic[TSource, TDestin]):
self.CleanNameAsADAWants(sp._id + "_" + subProgramImplementation + "_wrapper")) self.CleanNameAsADAWants(sp._id + "_" + subProgramImplementation + "_wrapper"))
else: else:
# Check if Function Block will exist both as SW and HW. If yes append suffix to avoid multiple definition errors.
fpgaSuffix = ''
if subProgramImplementation.lower() == "c" and sp._fpgaConfigurations is not '':
fpgaSuffix = "_Fpga"
self.C_HeaderFile.write("void Execute_%s();\n" % self.CleanNameAsADAWants(sp._id + "_" + subProgramImplementation)) self.C_HeaderFile.write("void Execute_%s();\n" % self.CleanNameAsADAWants(sp._id + "_" + subProgramImplementation))
if maybeFVname != "": if maybeFVname != "":
self.C_HeaderFile.write("void init_%s();\n" % (self.CleanNameAsADAWants(maybeFVname))) self.C_HeaderFile.write("void init_%s%s();\n" % (self.CleanNameAsADAWants(maybeFVname), fpgaSuffix))
self.C_HeaderFile.write("void %s_%s(" % (self.CleanNameAsADAWants(maybeFVname), self.CleanNameAsADAWants(sp._id))) self.C_HeaderFile.write("void %s_%s%s(" % (self.CleanNameAsADAWants(maybeFVname), self.CleanNameAsADAWants(sp._id), fpgaSuffix))
else: # pragma: no cover else: # pragma: no cover
self.C_HeaderFile.write("void %s_init();\n" % self.CleanNameAsADAWants(sp._id)) # pragma: no cover self.C_HeaderFile.write("void %s_init();\n" % self.CleanNameAsADAWants(sp._id)) # pragma: no cover
self.C_HeaderFile.write("void %s(" % self.CleanNameAsADAWants(sp._id)) # pragma: no cover self.C_HeaderFile.write("void %s(" % self.CleanNameAsADAWants(sp._id)) # pragma: no cover
...@@ -592,7 +597,7 @@ class SynchronousToolGlueGeneratorGeneric(Generic[TSource, TDestin]): ...@@ -592,7 +597,7 @@ class SynchronousToolGlueGeneratorGeneric(Generic[TSource, TDestin]):
self.C_SourceFile.write("}\n\n") self.C_SourceFile.write("}\n\n")
if maybeFVname != "": if maybeFVname != "":
self.C_SourceFile.write("void init_%s()\n" % self.CleanNameAsADAWants(maybeFVname)) self.C_SourceFile.write("void init_%s%s()\n" % (self.CleanNameAsADAWants(maybeFVname), fpgaSuffix))
else: # pragma: no cover else: # pragma: no cover
self.C_SourceFile.write("void %s_init()\n" % self.CleanNameAsADAWants(sp._id)) # pragma: no cover self.C_SourceFile.write("void %s_init()\n" % self.CleanNameAsADAWants(sp._id)) # pragma: no cover
self.C_SourceFile.write("{\n") self.C_SourceFile.write("{\n")
...@@ -601,7 +606,7 @@ class SynchronousToolGlueGeneratorGeneric(Generic[TSource, TDestin]): ...@@ -601,7 +606,7 @@ class SynchronousToolGlueGeneratorGeneric(Generic[TSource, TDestin]):
# self.C_SourceFile.write(" InitializeGlue();\n") # self.C_SourceFile.write(" InitializeGlue();\n")
self.C_SourceFile.write("}\n\n") self.C_SourceFile.write("}\n\n")
if maybeFVname != "": if maybeFVname != "":
self.C_SourceFile.write("void %s_%s(" % (self.CleanNameAsADAWants(maybeFVname), self.CleanNameAsADAWants(sp._id))) self.C_SourceFile.write("void %s_%s%s(" % (self.CleanNameAsADAWants(maybeFVname), self.CleanNameAsADAWants(sp._id), fpgaSuffix))
else: # pragma: no cover else: # pragma: no cover
self.C_SourceFile.write("void %s(" % self.CleanNameAsADAWants(sp._id)) # pragma: no cover self.C_SourceFile.write("void %s(" % self.CleanNameAsADAWants(sp._id)) # pragma: no cover
for param in sp._params: for param in sp._params:
......
...@@ -1333,6 +1333,7 @@ class Parser(antlr.LLkParser): ...@@ -1333,6 +1333,7 @@ class Parser(antlr.LLkParser):
if assoc._name[-19:].lower() == "fpga_configurations": if assoc._name[-19:].lower() == "fpga_configurations":
stripQuotes = assoc._value.replace("\"", "") stripQuotes = assoc._value.replace("\"", "")
g_subProgramImplementations[-1][4] = stripQuotes g_subProgramImplementations[-1][4] = stripQuotes
sp.SetFPGAConfigurations(stripQuotes)
self.match(END) self.match(END)
id = self.LT(1) id = self.LT(1)
self.match(IDENT) self.match(IDENT)
......
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