Commit 54fd68fc authored by Tiago Jorge's avatar Tiago Jorge
Browse files

Update generated Brave VHDL according to TASE simulation

parent 029c1cca
......@@ -79,7 +79,7 @@ def RegistersAllocated(node_or_str: Union[str, AsnNode]) -> int:
retValue = 0
realLeafType = asnParser.g_leafTypeDict[node._leafType]
if realLeafType == "INTEGER":
retValue = 8
retValue = 32
elif realLeafType == "REAL":
panic("The VHDL mapper can't work with REALs (non-synthesizeable circuits!) (%s)" % node.Location()) # pragma: no cover
elif realLeafType == "BOOLEAN":
......@@ -711,15 +711,15 @@ class MapASN1ToVHDLreadinputdata(RecursiveMapperGeneric[List[int], str]): # pyl
panicWithCallStack("INTEGERs need explicit ranges when generating VHDL code... (%s)" % node.Location()) # pragma: no cover
# bits = math.log(max(map(abs, node._range)+1),2)+(1 if node._range[0] < 0 else 0)
lines = [] # type: List[str]
lines.append('when X"%s" => %s( 7 downto 0) <= apbi.pwdata(7 downto 0);' % (hex(reginfo[0] + 0)[2:], dstVHDL))
lines.append('when X"%s" => %s(15 downto 8) <= apbi.pwdata(7 downto 0);' % (hex(reginfo[0] + 1)[2:], dstVHDL))
lines.append('when X"%s" => %s(23 downto 16) <= apbi.pwdata(7 downto 0);' % (hex(reginfo[0] + 2)[2:], dstVHDL))
lines.append('when X"%s" => %s(31 downto 24) <= apbi.pwdata(7 downto 0);' % (hex(reginfo[0] + 3)[2:], dstVHDL))
lines.append('when X"%s" => %s(39 downto 32) <= apbi.pwdata(7 downto 0);' % (hex(reginfo[0] + 4)[2:], dstVHDL))
lines.append('when X"%s" => %s(47 downto 40) <= apbi.pwdata(7 downto 0);' % (hex(reginfo[0] + 5)[2:], dstVHDL))
lines.append('when X"%s" => %s(55 downto 48) <= apbi.pwdata(7 downto 0);' % (hex(reginfo[0] + 6)[2:], dstVHDL))
lines.append('when X"%s" => %s(63 downto 56) <= apbi.pwdata(7 downto 0);' % (hex(reginfo[0] + 7)[2:], dstVHDL))
reginfo[0] += 8
lines.append('when X"%s" => %s( 7 downto 0) <= apbi.pwdata(7 downto 0);' % (hex(reginfo[0] + 0)[2:], dstVHDL))
lines.append('when X"%s" => %s(15 downto 8) <= apbi.pwdata(7 downto 0);' % (hex(reginfo[0] + 4)[2:], dstVHDL))
lines.append('when X"%s" => %s(23 downto 16) <= apbi.pwdata(7 downto 0);' % (hex(reginfo[0] + 8)[2:], dstVHDL))
lines.append('when X"%s" => %s(31 downto 24) <= apbi.pwdata(7 downto 0);' % (hex(reginfo[0] + 12)[2:], dstVHDL))
lines.append('when X"%s" => %s(39 downto 32) <= apbi.pwdata(7 downto 0);' % (hex(reginfo[0] + 16)[2:], dstVHDL))
lines.append('when X"%s" => %s(47 downto 40) <= apbi.pwdata(7 downto 0);' % (hex(reginfo[0] + 20)[2:], dstVHDL))
lines.append('when X"%s" => %s(55 downto 48) <= apbi.pwdata(7 downto 0);' % (hex(reginfo[0] + 24)[2:], dstVHDL))
lines.append('when X"%s" => %s(63 downto 56) <= apbi.pwdata(7 downto 0);' % (hex(reginfo[0] + 28)[2:], dstVHDL))
reginfo[0] += 32
return lines
def MapReal(self, _: List[int], __: str, node: AsnReal, ___: AST_Leaftypes, dummy: AST_Lookup) -> List[str]: # pylint: disable=invalid-sequence-index
......@@ -786,15 +786,15 @@ class MapASN1ToVHDLwriteoutputdata(RecursiveMapperGeneric[List[int], str]): # p
panicWithCallStack("INTEGERs need explicit ranges when generating VHDL code... (%s)" % node.Location()) # pragma: no cover
# bits = math.log(max(map(abs, node._range)+1),2)+(1 if node._range[0] < 0 else 0)
lines = [] # type: List[str]
lines.append('when X"%s" => apbo.prdata(7 downto 0) <= %s( 7 downto 0);' % (hex(reginfo[0] + 0)[2:], dstVHDL))
lines.append('when X"%s" => apbo.prdata(7 downto 0) <= %s(15 downto 8);' % (hex(reginfo[0] + 1)[2:], dstVHDL))
lines.append('when X"%s" => apbo.prdata(7 downto 0) <= %s(23 downto 16);' % (hex(reginfo[0] + 2)[2:], dstVHDL))
lines.append('when X"%s" => apbo.prdata(7 downto 0) <= %s(31 downto 24);' % (hex(reginfo[0] + 3)[2:], dstVHDL))
lines.append('when X"%s" => apbo.prdata(7 downto 0) <= %s(39 downto 32);' % (hex(reginfo[0] + 4)[2:], dstVHDL))
lines.append('when X"%s" => apbo.prdata(7 downto 0) <= %s(47 downto 40);' % (hex(reginfo[0] + 5)[2:], dstVHDL))
lines.append('when X"%s" => apbo.prdata(7 downto 0) <= %s(55 downto 48);' % (hex(reginfo[0] + 6)[2:], dstVHDL))
lines.append('when X"%s" => apbo.prdata(7 downto 0) <= %s(63 downto 56);' % (hex(reginfo[0] + 7)[2:], dstVHDL))
reginfo[0] += 8
lines.append('when X"%s" => apbo.prdata(7 downto 0) <= %s( 7 downto 0);' % (hex(reginfo[0] + 0)[2:], dstVHDL))
lines.append('when X"%s" => apbo.prdata(7 downto 0) <= %s(15 downto 8);' % (hex(reginfo[0] + 4)[2:], dstVHDL))
lines.append('when X"%s" => apbo.prdata(7 downto 0) <= %s(23 downto 16);' % (hex(reginfo[0] + 8)[2:], dstVHDL))
lines.append('when X"%s" => apbo.prdata(7 downto 0) <= %s(31 downto 24);' % (hex(reginfo[0] + 12)[2:], dstVHDL))
lines.append('when X"%s" => apbo.prdata(7 downto 0) <= %s(39 downto 32);' % (hex(reginfo[0] + 16)[2:], dstVHDL))
lines.append('when X"%s" => apbo.prdata(7 downto 0) <= %s(47 downto 40);' % (hex(reginfo[0] + 20)[2:], dstVHDL))
lines.append('when X"%s" => apbo.prdata(7 downto 0) <= %s(55 downto 48);' % (hex(reginfo[0] + 24)[2:], dstVHDL))
lines.append('when X"%s" => apbo.prdata(7 downto 0) <= %s(63 downto 56);' % (hex(reginfo[0] + 28)[2:], dstVHDL))
reginfo[0] += 32
return lines
def MapReal(self, _: List[int], __: str, node: AsnReal, ___: AST_Leaftypes, dummy: AST_Lookup) -> List[str]: # pylint: disable=invalid-sequence-index
......@@ -1058,12 +1058,12 @@ def OnFinal() -> None:
readinputdataLines = []
readinputdataLines.append("\n" + ' ' * 22 + '-- kickoff ' + c._spCleanName)
kickoffWriteAccess = "when X\"%(off)s\" => %(pi)s_StartCalculationsInternal <= %(pi)s_StartCalculationsInternal xor '1';\n" % {'pi': c._spCleanName, 'off': hex(0x0300 + c._offset)[2:]}
kickoffWriteAccess = "when X\"%(off)s\" => %(pi)s_StartCalculationsInternal <= %(pi)s_StartCalculationsInternal xor '1';\n" % {'pi': c._spCleanName, 'off': hex(0x300 + c._offset)[2:]}
readinputdataLines.append(kickoffWriteAccess)
connectionsToSystemCLines = []
counter = cast(List[int], [0x0300 + c._offset + 1]) # type: List[int] # pylint: disable=invalid-sequence-index
counter = cast(List[int], [0x300 + c._offset + 4]) # type: List[int] # pylint: disable=invalid-sequence-index
for p in c._sp._params:
node = VHDL_Circuit.names[p._signal._asnNodename]
direction = "in " if isinstance(p, InParam) else "out "
......@@ -1088,7 +1088,7 @@ def OnFinal() -> None:
writeoutputdataLines = []
writeoutputdataLines.append("\n" + ' ' * 16 + '-- result calculated flag ' + c._spCleanName)
accessCompletionFlag = "when X\"%(off)s\" => apbo.prdata(7 downto 0) <= \"0000000\" & %(pi)s_CalculationsComplete;\n" % \
{'pi': c._spCleanName, 'off': hex(0x0300 + c._offset)[2:]}
{'pi': c._spCleanName, 'off': hex(0x300 + c._offset)[2:]}
writeoutputdataLines.append(accessCompletionFlag)
for p in c._sp._params:
......@@ -1138,7 +1138,10 @@ def OnFinal() -> None:
''' % {'pi': c._spCleanName})
AddToStr('reset', " %(pi)s_StartCalculationsInternal <= '0';\n" % {'pi': c._spCleanName})
AddToStr('reset', " %(pi)s_StartCalculationsInternal <= '0';\n" % {'pi': c._spCleanName})
AddToStr('reset', " --%(pi)s_inp <= (others => '0');\n" % {'pi': c._spCleanName})
AddToStr('reset', " %(pi)s_StartCalculationsPulse <= '0';\n" % {'pi': c._spCleanName})
AddToStr('reset', " %(pi)s_StartCalculationsInternalOld <= '0';\n" % {'pi': c._spCleanName})
AddToStr('updateStartStopPulses',
' %(pi)s_StartCalculationsPulse <= %(pi)s_StartCalculationsInternal xor %(pi)s_StartCalculationsInternalOld;\n' % {'pi': c._spCleanName})
AddToStr('updateStartStopPulses',
......
......@@ -37,13 +37,18 @@
#
# Charge for Runtimes None None
#
vhd = '''library ieee;
vhd = '''-- Company: GMV
-- Copyright European Space Agency, 2018
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library leon2ft;
use leon2ft.amba.all;
library tase;
entity TASTE is
port (
clk_i : in std_logic; -- System clock
......@@ -69,7 +74,7 @@ begin
-- Implement register write
process (reset_n, clk_i)
begin
if (reset_n='1') then
if (reset_n='0') then
-- Signals for reset
%(reset)s
elsif (clk_i'event and clk_i='1') then
......@@ -86,17 +91,15 @@ begin
end process;
-- Implement register read
process (apbi.paddr, apbi.pwrite, %(outputs)s %(completions)s)
process (apbi.paddr, apbi.pwrite, apbi.psel, %(outputs)s %(completions)s)
begin
apbo.prdata <= (others => '0');
if (apbi.pwrite='0' and apbi.psel= '1') then
case (apbi.paddr(11 downto 0)) is
-- Write data
%(writeoutputdata)s
when others => apbo.prdata(7 downto 0) <= (others => '0');
end case;
else
-- avoid latches
apbo.prdata(7 downto 0) <= (others => '0');
end if;
end process;
......@@ -122,7 +125,9 @@ clean:
%(tab)srm -rf logs *.nxm *.pyc *.nxb
'''
per_circuit_vhd = """
per_circuit_vhd = """-- Company: GMV
-- Copyright European Space Agency, 2018
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
......@@ -150,8 +155,10 @@ begin
-- Possible clock divider
process(CLK, RST)
begin
if (RST='1') then
finish_%(pi)s <= '1';
if (RST='0') then
finish_%(pi)s <= '0'; -- or 1?
state <= wait_for_start_signal;
-- outp <= (others => '0');
elsif (CLK'event and CLK='1') then
case state is
when wait_for_start_signal =>
......
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