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dmt
Commits
46f67a31
Commit
46f67a31
authored
Sep 24, 2019
by
Patricia Lopez Cueva
Browse files
Missing ManageAsynchronousReadPort option on synthesis
parent
bee78070
Changes
1
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dmt/B_mappers/vhdlTemplateBrave.py
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46f67a31
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@@ -316,6 +316,7 @@ project.setOptions({'UseNxLibrary': 'Yes',
'MergeRegisterToPad': 'Always',
'ManageUnconnectedOutputs': 'Ground',
'ManageUnconnectedSignals': 'Ground',
'ManageAsynchronousReadPort': 'Yes',
'DefaultRAMMapping': 'RAM'})
project.addMappingDirective('getModels(.*regfile_3p.*)', 'RAM', 'RF')
#=======================================================================================================
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