Commit 06b7a7a5 authored by Laura Alexandra Sequeira Gouveia's avatar Laura Alexandra Sequeira Gouveia
Browse files

Zynq mapper: generate programming scripts for ZynQ-7000

parent b35a3765
......@@ -1036,6 +1036,46 @@ clean:
%(tab)srm -rf *.bit
'''
load_exec = r'''
#! /bin/bash
#Get the programming script path
TCL_DIR="$( cd "$( dirname "$0" )" >/dev/null 2>&1 && pwd )"
#Call the script
/tools/Xilinx/Vivado/2019.2/bin/xsdb $TCL_DIR/programming.tcl $TCL_DIR $1
'''
programming_tcl = r'''
set host_ip 172.22.71.42
set host_port 3121
set path [lindex $argv 0]
cd $path
puts -nonewline "Connecting to ${host_ip}:${host_port}..."
connect -host 172.22.71.42 -port 3121
puts "OK!"
targets
targets 2
puts -nonewline "Reset the system..."
rst -system
puts "OK!"
puts "Load FPGA and configuring PS system"
fpga -f TASTE/TASTE.runs/impl_1/TASTE_wrapper.bit
source TASTE/TASTE.srcs/sources_1/bd/TASTE/ip/TASTE_processing_system7_0_0/ps7_init.tcl
ps7_init
ps7_post_config
puts "Load FPGA and configuring PS system OK!"
eval dow [lindex $argv 1]
con
##Uncomment if it is deseired to run in two targets
##targets 3
##con -addr 0x00404040
puts "Software is running!"
'''
axi_support = r'''
#define ARM_CP15_TEXT_SECTION BSP_START_TEXT_SECTION
......
......@@ -2065,7 +2065,15 @@ def OnFinal() -> None:
makefile = open(vhdlBackend.dir + '/TASTE-VHDL-DESIGN/project/Makefile', 'w')
makefile.write(vhdlTemplateZynQZC706.makefile % {'pi': msg, 'tab': '\t'})
makefile.close()
load_exec = open(vhdlBackend.dir + '/TASTE-VHDL-DESIGN/project/load_exec.sh', 'w')
load_exec.write(vhdlTemplateZynQZC706.load_exec)
load_exec.close()
programming_tcl = open(vhdlBackend.dir + '/TASTE-VHDL-DESIGN/project/programming.tcl', 'w')
programming_tcl.write(vhdlTemplateZynQZC706.programming_tcl)
programming_tcl.close()
axi_support = open(vhdlBackend.dir + '/axi_support.h', 'w')
axi_support.write(vhdlTemplateZynQZC706.axi_support)
axi_support.close()
......
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