vhdlTemplateZynQZC706.py 43.7 KB
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# Company: GMV
# Copyright European Space Agency, 2019-2020

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vhd = '''--------------------------------------------------------------------------------
-- Company: GMV Aerospace & Defence S.A.U.
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-- Copyright European Space Agency, 2019-2020
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--------------------------------------------------------------------------------
--   __ _ _ __ _____   __
--  / _` | '_ ` _ \ \ / /   Company:	GMV Aerospace & Defence S.A.U.
-- | (_| | | | | | \ V /    Author: 	Ruben Domingo Torrijos (rdto@gmv.com)
--  \__, |_| |_| |_|\_/     Module: 	TASTE
--   __/ |               
--  |___/              
-- 
-- Create Date: 18/09/2019
-- Design Name: TASTE
-- Module Name: TASTE
-- Project Name: Cora-mbad-4zynq
-- Target Devices: XC7Z045
-- Tool versions: Vivado 2019
-- Description: Interface between Zynq proccesor and Bambu IP through AXI_LITE
--
-- Dependencies:
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity TASTE is
    port (
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		---------------------------------------------------
		--			  AXI4 LITE CORE CONTROLLER 		 --
		---------------------------------------------------
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		-- Clock and Reset
		S_AXI_ACLK				: in  std_logic;
		S_AXI_ARESETN			: in  std_logic;
		-- Write Address Channel
		S_AXI_AWADDR			: in  std_logic_vector(31 downto 0);
		S_AXI_AWVALID			: in  std_logic;
		S_AXI_AWREADY			: out std_logic;
		-- Write Data Channel
		S_AXI_WDATA				: in  std_logic_vector(31 downto 0);
		S_AXI_WSTRB				: in  std_logic_vector(3 downto 0);
		S_AXI_WVALID			: in  std_logic;
		S_AXI_WREADY			: out std_logic;
		-- Read Address Channel
		S_AXI_ARADDR			: in  std_logic_vector(31 downto 0);
		S_AXI_ARVALID			: in  std_logic;
		S_AXI_ARREADY			: out std_logic;
		-- Read Data Channel
		S_AXI_RDATA				: out std_logic_vector(31 downto 0);
		S_AXI_RRESP				: out std_logic_vector(1 downto 0);
		S_AXI_RVALID			: out std_logic;
		S_AXI_RREADY			: in  std_logic;
		-- Write Response Channel
		S_AXI_BRESP				: out std_logic_vector(1 downto 0);
		S_AXI_BVALID			: out std_logic;
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		S_AXI_BREADY			: in  std_logic
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    );
end TASTE;

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architecture rtl of TASTE is
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	---------------------------------------------------
	--			  COMPONENT DECLARATION			 	 --
	---------------------------------------------------	
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    -- Circuits for the existing PIs
%(circuits)s
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	---------------------------------------------------
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	--			  CONSTANTS			 	 	 		 --
	---------------------------------------------------
	
	constant OKAY						: std_logic_vector(1 downto 0) 		:= "00";
	constant EXOKAY						: std_logic_vector(1 downto 0) 		:= "01";
	constant SLVERR						: std_logic_vector(1 downto 0) 		:= "10";
	constant DECERR						: std_logic_vector(1 downto 0) 		:= "11";
	

	----------------------------------------------------
	--			  	TYPE DEFINITION			 	 	  --
	----------------------------------------------------

	------------------------------
	--	AXI LITE SLAVE CTRL		--
	------------------------------
	-- AXI4 LITE SLAVE CONTROLLER FSM --
	type AXI_SLAVE_CTRL_states is(idle, reading, r_complete, writing, wait_resp);
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	-- AXI4 combinational outputs record --
	type AXI_SLAVE_CTRL_comb_out is record		
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		awready			: std_logic;
		wready			: std_logic;
		arready			: std_logic;
		rdata			: std_logic_vector(31 downto 0);
		rresp			: std_logic_vector(1 downto 0);
		rvalid			: std_logic;
		bvalid			: std_logic;
	
	end record;
	
	-- AXI4 internal signals record --
	type AXI_SLAVE_CTRL_inter is record
	
		current_state			: AXI_SLAVE_CTRL_states;
		r_local_address			: integer;
		bresp					: std_logic_vector(1 downto 0);
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        --Registers for I/O
        %(inputdeclaration)s
        done					: std_logic;
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	end record;
	
	constant INIT_AXI_SLAVE_CTRL_comb_out	: AXI_SLAVE_CTRL_comb_out	:= (awready		=> '0',	
																			wready		=> '0',
																			arready		=> '0',
																			rdata		=> (others => '0'),
																			rresp		=> OKAY,
																			rvalid		=> '0',
																			bvalid		=> '0'
																			);
																						
	constant INIT_AXI_SLAVE_CTRL_inter	: AXI_SLAVE_CTRL_inter 		:= (current_state		=> idle,
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										r_local_address		=> 0,
										bresp				=> OKAY,
										--Registers for I/O
                                        %(inputassign)s
                                        done                => '0'
                                                                                );
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	------------------------------
	--	SIGNAL DECLARATION		--
	------------------------------	
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    -- Registers for I/O
%(ioregisters)s

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	-- AXI LITE SLAVE CTRL Signals --	
	signal AXI_SLAVE_CTRL_r					: AXI_SLAVE_CTRL_inter;
	signal AXI_SLAVE_CTRL_rin				: AXI_SLAVE_CTRL_inter;
	signal AXI_SLAVE_CTRL_r_comb_out		: AXI_SLAVE_CTRL_comb_out;
	signal AXI_SLAVE_CTRL_rin_comb_out		: AXI_SLAVE_CTRL_comb_out;
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begin

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	---------------------------------------------------
	--				COMPONENT INSTANTITATION		 --
	---------------------------------------------------
    -- Connections to the VHDL circuits
%(connectionsToSystemC)s

	---------------------------------------------------
	--				PROCESS INSTANTIATION		     --
	---------------------------------------------------		
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	---------------------------------------------------
	--				AXI LITE SLAVE CTRL			 	 --
	---------------------------------------------------	
	-- Sequential process --
	seq_axi_slave:	process(S_AXI_ACLK)
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	begin 		
		if rising_edge(S_AXI_ACLK) then
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			AXI_SLAVE_CTRL_r				<= AXI_SLAVE_CTRL_rin;
			AXI_SLAVE_CTRL_r_comb_out		<= AXI_SLAVE_CTRL_rin_comb_out;
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		end if;
	end process;
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	-- Combinational process --	
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	comb_axi_slave: process(	-- internal signals --
							AXI_SLAVE_CTRL_r, AXI_SLAVE_CTRL_r_comb_out,
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							-- AXI inptuts --
							S_AXI_ARESETN, S_AXI_AWADDR, S_AXI_AWVALID, S_AXI_WDATA, S_AXI_WSTRB, S_AXI_WVALID, S_AXI_ARADDR, S_AXI_ARVALID, S_AXI_RREADY, S_AXI_BREADY,
							-- Bambu signals --
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							%(outputs)s,
							%(completions)s,
							%(starts)s
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							)
							
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		variable v									: AXI_SLAVE_CTRL_inter;
		variable v_comb_out							: AXI_SLAVE_CTRL_comb_out;
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		variable comb_S_AXI_AWVALID_S_AXI_ARVALID	: std_logic_vector(1 downto 0);
		variable w_local_address					: integer;
		
	begin
	
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		-----------------------------------------------------------------
		--				   DEFAULT VARIABLES ASIGNATION		           --
		-----------------------------------------------------------------
		v 											:= AXI_SLAVE_CTRL_r;		
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		-----------------------------------------------------------------
		--	 	DEFAULT COMBINATIONAL OUTPUT VARIABLES ASIGNATION      --
		-----------------------------------------------------------------
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		v_comb_out									:= INIT_AXI_SLAVE_CTRL_comb_out;
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                %(done_start_assign)s
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		-----------------------------------------------------------------
		--	 			DEFAULT INTERNAL VARIABLE ASIGNATION      	   --
		-----------------------------------------------------------------		
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		w_local_address								:= to_integer(unsigned(S_AXI_AWADDR(15 downto 0)));
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		comb_S_AXI_AWVALID_S_AXI_ARVALID			:= S_AXI_AWVALID&S_AXI_ARVALID;	
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                -- Update start-stop pulses
                %(starstoppulses)s
                -----------------------------------------------------------------
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		--	 					 AXI LITE CTRL FSM      	   		   --
		-----------------------------------------------------------------		
		case AXI_SLAVE_CTRL_r.current_state is
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			when idle =>
				v.bresp					:= OKAY;
				case comb_S_AXI_AWVALID_S_AXI_ARVALID is
					when "01" 	=> 
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						v.current_state 	:= reading;
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					when "11" 	=> 
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						v.current_state 	:= reading;
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					when "10" 	=> 
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						v.current_state 	:= writing;
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					when others	=> 
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						v.current_state 	:= idle;
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				end case;			
			
			when writing =>
				v_comb_out.awready		:= S_AXI_AWVALID;
				v_comb_out.wready		:= S_AXI_WVALID;
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				v.bresp					:= AXI_SLAVE_CTRL_r.bresp;				
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				if S_AXI_WVALID = '1' then
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					v.current_state	:= wait_resp;
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					case w_local_address is
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                        %(readinputdata)s
						when others => null;
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					end case;
				end if;
				
			when wait_resp =>
				v_comb_out.awready		:= S_AXI_AWVALID;
				v_comb_out.wready		:= S_AXI_WVALID;
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				v.bresp					:= AXI_SLAVE_CTRL_r.bresp;
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				v_comb_out.bvalid		:= S_AXI_BREADY;
				if S_AXI_AWVALID = '0' then
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					v.current_state := idle;
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				else
					if S_AXI_WVALID = '1' then
						case w_local_address is
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                        %(readinputdata)s
							when others => null;
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						end case;
					else
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						v.current_state := writing;
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					end if;
				end if;
			
			when reading =>
				v_comb_out.arready		:= S_AXI_ARVALID;
				v.bresp					:= OKAY;
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				v.r_local_address		:= to_integer(unsigned(S_AXI_ARADDR(15 downto 0)));
				v.current_state 		:= r_complete;
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			when r_complete => 
				v_comb_out.arready		:= S_AXI_ARVALID;
				v_comb_out.rvalid		:= '1';
				v.bresp					:= OKAY;
				if S_AXI_RREADY = '1' then
					if S_AXI_ARVALID = '0' then
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						v.current_state 	:= idle;
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					else
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						v.r_local_address	:= to_integer(unsigned(S_AXI_ARADDR(15 downto 0)));
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					end if;
				end if;
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				case AXI_SLAVE_CTRL_r.r_local_address is
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					-- result calculated flag
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                    %(writeoutputdata)s
					when others => v_comb_out.rdata(31 downto 0) 	:= (others => '0');								
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				end case;
		end case;
		---------------------------------------------------
		--				  RESET ASIGNATION		 	     --
		---------------------------------------------------		
		if S_AXI_ARESETN = '0' then
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			v		    			:= INIT_AXI_SLAVE_CTRL_inter;
			v_comb_out				:= INIT_AXI_SLAVE_CTRL_comb_out;
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		end if;
		---------------------------------------------------
		--				SIGNAL ASIGNATION			     --
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		---------------------------------------------------
		AXI_SLAVE_CTRL_rin 	       	<= v;
		AXI_SLAVE_CTRL_rin_comb_out	<= v_comb_out;
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	end process;
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	----------------------------------------------------------
	--			          OUTPUTS	 	 	    		 	--
	----------------------------------------------------------
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        %(internalsignals)s	

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	---------------------------------------------------
	--				AXI LITE SLAVE CTRL			 	 --
	---------------------------------------------------		
	S_AXI_AWREADY			<= AXI_SLAVE_CTRL_rin_comb_out.awready;
	S_AXI_WREADY			<= AXI_SLAVE_CTRL_rin_comb_out.wready;
	S_AXI_ARREADY			<= AXI_SLAVE_CTRL_rin_comb_out.arready;
	S_AXI_RDATA				<= AXI_SLAVE_CTRL_rin_comb_out.rdata;
	S_AXI_RRESP				<= AXI_SLAVE_CTRL_rin_comb_out.rresp;
	S_AXI_RVALID			<= AXI_SLAVE_CTRL_rin_comb_out.rvalid;
	S_AXI_BRESP				<= AXI_SLAVE_CTRL_rin.bresp;
	S_AXI_BVALID			<= AXI_SLAVE_CTRL_rin_comb_out.bvalid;
	
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end rtl;'''
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makefile = r'''
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SRCS=../ip/src/TASTE_AXI.vhd ../ip/src/%(pi)s
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all:   ${SRCS}
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%(tab)svivado -mode batch -source TASTE_AXI.tcl
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clean:
%(tab)srm -rf *.bit
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'''

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axi_support = r'''
#define ARM_CP15_TEXT_SECTION BSP_START_TEXT_SECTION

#include <bsp.h>
#include <bsp/start.h>
#include <bsp/arm-gic-irq.h>
#include <bsp/arm-cp15-start.h>
#include <bsp/arm-a9mpcore-start.h>


#ifdef ARMV7_CP15_START_DEFAULT_SECTIONS

BSP_START_DATA_SECTION static const arm_cp15_start_section_config zynq_mmu_config_table[] = {
    ARMV7_CP15_START_DEFAULT_SECTIONS,
    {
    .begin = 0xe0000000U,
    .end   = 0xe0200000U,
    .flags = ARMV7_MMU_DEVICE
    }, {
    .begin = 0xf8000000U,
    .end   = 0xf9000000U,
    .flags = ARMV7_MMU_DEVICE
    }, {
    .begin = 0x40000000U,
    .end   = 0xc0000000U,
    .flags = ARMV7_MMU_DEVICE
    }, {
    .begin = 0x00100000U,
    .end   = 0x00400000U,
    .flags = ARMV7_MMU_DEVICE
    }, {
    .begin = 0xfffc0000u,
    .end   = 0xffffffffu,
    .flags = ARMV7_MMU_DEVICE
    }
};

BSP_START_TEXT_SECTION void zynq_setup_mmu_and_cache(void) {
    uint32_t ctrl = arm_cp15_start_setup_mmu_and_cache(
    ARM_CP15_CTRL_A,
    ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
    );

    arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache(
    ctrl,
    (uint32_t *) bsp_translation_table_base,
    ARM_MMU_DEFAULT_CLIENT_DOMAIN,
    &zynq_mmu_config_table[0],
    RTEMS_ARRAY_SIZE(zynq_mmu_config_table)
    );
}

#pragma message ("Memory configurations updated for AXI interfaces")

#endif
'''

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per_circuit_vhd = """-- Company: GMV
-- Copyright European Space Agency, 2019-2020

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

%(declaration)s

architecture arch of bambu_%(pi)s is

    -- Declare signals
    signal CLK : std_logic;
    signal RST : std_logic;

    signal state : unsigned(1 downto 0);
begin

    CLK <= clock_%(pi)s;
    RST <= reset_%(pi)s;

    -- Possible clock divider
    process(CLK, RST)
    begin
        if (RST='0') then
            finish_%(pi)s <= '0'; -- or 1?
            state                    <= "00";
            -- outp                     <= (others => '0');
        elsif (CLK'event and CLK='1') then
            case state is
                when "00" =>
                    if start_%(pi)s = '1' then
                        state <= "01";
                        finish_%(pi)s <= '0';
                    end if;
                when "01" =>

                    -----------------------------
                    -- Do your processing here --
                    -----------------------------

                    state <= "10";
                when "10" =>
                    finish_%(pi)s <= '1';
                    state <= "00";
                when others =>
                  state <= "00";
            end case;
        end if;
    end process;

end arch;
"""

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component_xml = """<?xml version="1.0" encoding="UTF-8"?>
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
  <spirit:vendor>user.org</spirit:vendor>
  <spirit:library>user</spirit:library>
  <spirit:name>TASTE</spirit:name>
  <spirit:version>1.0</spirit:version>
  <spirit:busInterfaces>
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    <spirit:busInterface>
      <spirit:name>S_AXIS</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>TDEST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>S_AXIS_TDEST</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>TDATA</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>S_AXIS_TDATA</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>TLAST</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>S_AXIS_TLAST</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>TVALID</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>S_AXIS_TVALID</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>TREADY</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>S_AXIS_TREADY</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
    </spirit:busInterface>
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    <spirit:busInterface>
      <spirit:name>S_AXI</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
      <spirit:slave>
        <spirit:memoryMapRef spirit:memoryMapRef="S_AXI"/>
      </spirit:slave>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>AWADDR</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>S_AXI_AWADDR</spirit:name>
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