Commit e02c0860 authored by Guilherme Sanches's avatar Guilherme Sanches

Header files belonging to the can driver included

parent 76b7b882
/*
* Header file for RTEMS CAN_MUX driver
*
* COPYRIGHT (c) 2008.
* Cobham Gaisler AB.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef __CANMUX_H__
#define __CANMUX_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Driver interface */
int canmux_register(void);
/* ioctl calls */
#define CANMUX_IOC_BUSA_SATCAN 1
#define CANMUX_IOC_BUSA_OCCAN1 2
#define CANMUX_IOC_BUSB_SATCAN 3
#define CANMUX_IOC_BUSB_OCCAN2 4
#ifdef __cplusplus
}
#endif
#endif /* __CANMUX_H__ */
/**
* @file
* @ingroup sparc_bsp
* @defgroup can GRCAN
* @ingroup can
* @brief Macros used for grcan controller
*/
/*
* COPYRIGHT (c) 2007.
* Cobham Gaisler AB.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef __GRCAN_H__
#define __GRCAN_H__
#ifdef __cplusplus
extern "C" {
#endif
struct grcan_regs {
volatile unsigned int conf; /* 0x00 */
volatile unsigned int stat; /* 0x04 */
volatile unsigned int ctrl; /* 0x08 */
volatile unsigned int dummy0[3]; /* 0x0C-0x014 */
volatile unsigned int smask; /* 0x18 */
volatile unsigned int scode; /* 0x1C */
volatile unsigned int dummy1[56]; /* 0x20-0xFC */
volatile unsigned int pimsr; /* 0x100 */
volatile unsigned int pimr; /* 0x104 */
volatile unsigned int pisr; /* 0x108 */
volatile unsigned int pir; /* 0x10C */
volatile unsigned int imr; /* 0x110 */
volatile unsigned int picr; /* 0x114 */
volatile unsigned int dummy2[58]; /* 0x118-0x1FC */
volatile unsigned int tx0ctrl; /* 0x200 */
volatile unsigned int tx0addr; /* 0x204 */
volatile unsigned int tx0size; /* 0x208 */
volatile unsigned int tx0wr; /* 0x20C */
volatile unsigned int tx0rd; /* 0x210 */
volatile unsigned int tx0irq; /* 0x214 */
volatile unsigned int dummy3[58]; /* 0x218-0x2FC */
volatile unsigned int rx0ctrl; /* 0x300 */
volatile unsigned int rx0addr; /* 0x304 */
volatile unsigned int rx0size; /* 0x308 */
volatile unsigned int rx0wr; /* 0x30C */
volatile unsigned int rx0rd; /* 0x310 */
volatile unsigned int rx0irq; /* 0x314 */
volatile unsigned int rx0mask; /* 0x318 */
volatile unsigned int rx0code; /* 0x31C */
};
struct grcan_stats {
unsigned int passive_cnt;
unsigned int overrun_cnt;
unsigned int rxsync_cnt;
unsigned int txsync_cnt;
unsigned int txloss_cnt;
unsigned int ahberr_cnt;
unsigned int ints;
};
struct grcan_timing {
unsigned char scaler;
unsigned char ps1;
unsigned char ps2;
unsigned int rsj;
unsigned char bpr;
};
struct grcan_selection {
int selection;
int enable0;
int enable1;
};
struct grcan_filter {
unsigned long long mask;
unsigned long long code;
};
/* CAN MESSAGE */
typedef struct {
char extended; /* 1= Extended Frame (29-bit id), 0= STD Frame (11-bit id) */
char rtr; /* RTR - Remote Transmission Request */
char unused; /* unused */
unsigned char len;
unsigned char data[8];
unsigned int id;
} CANMsg;
#define GRCAN_CFG_ABORT 0x00000001
#define GRCAN_CFG_ENABLE0 0x00000002
#define GRCAN_CFG_ENABLE1 0x00000004
#define GRCAN_CFG_SELECTION 0x00000008
#define GRCAN_CFG_SILENT 0x00000010
#define GRCAN_CFG_BPR 0x00000300
#define GRCAN_CFG_RSJ 0x00007000
#define GRCAN_CFG_PS1 0x00f00000
#define GRCAN_CFG_PS2 0x000f0000
#define GRCAN_CFG_SCALER 0xff000000
#define GRCAN_CFG_BPR_BIT 8
#define GRCAN_CFG_RSJ_BIT 12
#define GRCAN_CFG_PS1_BIT 20
#define GRCAN_CFG_PS2_BIT 16
#define GRCAN_CFG_SCALER_BIT 24
#define GRCAN_CTRL_RESET 0x2
#define GRCAN_CTRL_ENABLE 0x1
#define GRCAN_TXCTRL_ENABLE 1
#define GRCAN_TXCTRL_ONGOING 1
#define GRCAN_RXCTRL_ENABLE 1
#define GRCAN_RXCTRL_ONGOING 1
/* Relative offset of IRQ sources to AMBA Plug&Play */
#define GRCAN_IRQ_IRQ 0
#define GRCAN_IRQ_TXSYNC 1
#define GRCAN_IRQ_RXSYNC 2
#define GRCAN_ERR_IRQ 0x1
#define GRCAN_OFF_IRQ 0x2
#define GRCAN_OR_IRQ 0x4
#define GRCAN_RXAHBERR_IRQ 0x8
#define GRCAN_TXAHBERR_IRQ 0x10
#define GRCAN_RXIRQ_IRQ 0x20
#define GRCAN_TXIRQ_IRQ 0x40
#define GRCAN_RXFULL_IRQ 0x80
#define GRCAN_TXEMPTY_IRQ 0x100
#define GRCAN_RX_IRQ 0x200
#define GRCAN_TX_IRQ 0x400
#define GRCAN_RXSYNC_IRQ 0x800
#define GRCAN_TXSYNC_IRQ 0x1000
#define GRCAN_RXERR_IRQ 0x2000
#define GRCAN_TXERR_IRQ 0x4000
#define GRCAN_RXMISS_IRQ 0x8000
#define GRCAN_TXLOSS_IRQ 0x10000
#define GRCAN_STAT_PASS 0x1
#define GRCAN_STAT_OFF 0x2
#define GRCAN_STAT_OR 0x4
#define GRCAN_STAT_AHBERR 0x8
#define GRCAN_STAT_ACTIVE 0x10
#define GRCAN_STAT_RXERRCNT 0xff00
#define GRCAN_STAT_TXERRCNT 0xff0000
/* IOCTL Commands controlling operational
* mode
*/
#define GRCAN_IOC_START 1 /* Bring the link up after open or bus-off */
#define GRCAN_IOC_STOP 2 /* stop to change baud rate/config or closing down */
#define GRCAN_IOC_ISSTARTED 3 /* return RTEMS_SUCCESSFUL when started, othervise EBUSY */
#define GRCAN_IOC_FLUSH 4 /* Waits until all TX messages has been sent */
/* IOCTL Commands that require connection
* to be stopped
*/
#define GRCAN_IOC_SET_SILENT 16 /* enable silent mode read only state */
#define GRCAN_IOC_SET_ABORT 17 /* enable/disable stopping link on AHB Error */
#define GRCAN_IOC_SET_SELECTION 18 /* Set Enable0,Enable1,Selection */
#define GRCAN_IOC_SET_SPEED 19 /* Set baudrate by using driver's baud rate timing calculation routines */
#define GRCAN_IOC_SET_BTRS 20 /* Set baudrate by specifying the timing registers manually */
/* IOCTL Commands can be called whenever */
#define GRCAN_IOC_SET_RXBLOCK 32 /* Enable/disable Blocking on reception (until at least one message has been received) */
#define GRCAN_IOC_SET_TXBLOCK 33 /* Enable/disable Blocking on transmission (until at least one message has been transmitted) */
#define GRCAN_IOC_SET_TXCOMPLETE 34 /* Enable/disable Blocking until all requested messages has been sent */
#define GRCAN_IOC_SET_RXCOMPLETE 35 /* Enable/disable Blocking until all requested has been received */
#define GRCAN_IOC_GET_STATS 36 /* Get Statistics */
#define GRCAN_IOC_CLR_STATS 37 /* Clear Statistics */
#define GRCAN_IOC_SET_AFILTER 38 /* Set Acceptance filters, provide pointer to "struct grcan_filter" or NULL to disable filtering (let all messages pass) */
#define GRCAN_IOC_SET_SFILTER 40 /* Set Sync Messages RX/TX filters, NULL disables the IRQ completely */
#define GRCAN_IOC_GET_STATUS 41 /* Get status register of GRCAN core */
void grcan_register_drv(void);
#ifdef __cplusplus
}
#endif
#endif
/**
* @file
* @ingroup can
* @brief Gaisler wrapper to OpenCores CAN - driver interface
*/
/*
* COPYRIGHT (c) 2007.
* Cobham Gaisler AB.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef __OCCAN_DRIVER_H__
#define __OCCAN_DRIVER_H__
#ifdef __cplusplus
extern "C" {
#endif
/* CAN MESSAGE */
typedef struct {
char extended; /* 1= Extended Frame (29-bit id), 0= STD Frame (11-bit id) */
char rtr; /* RTR - Remote Transmission Request */
char sshot; /* single shot */
unsigned char len;
unsigned char data[8];
unsigned int id;
} CANMsg;
typedef struct {
/* tx/rx stats */
unsigned int rx_msgs;
unsigned int tx_msgs;
/* Error Interrupt counters */
unsigned int err_warn;
unsigned int err_dovr;
unsigned int err_errp;
unsigned int err_arb;
unsigned int err_bus;
/**** BUS ERRORS (err_arb) ****/
/* ALC 4-0 */
unsigned int err_arb_bitnum[32]; /* At what bit arbitration is lost */
/******************************/
/**** BUS ERRORS (err_bus) ****/
/* ECC 7-6 */
unsigned int err_bus_bit; /* Bit error */
unsigned int err_bus_form; /* Form Error */
unsigned int err_bus_stuff; /* Stuff Error */
unsigned int err_bus_other; /* Other Error */
/* ECC 5 */
unsigned int err_bus_rx; /* Errors during Reception */
unsigned int err_bus_tx; /* Errors during Transmission */
/* ECC 4:0 */
unsigned int err_bus_segs[32]; /* Segment (Where in frame error occured)
* See OCCAN_SEG_* defines for indexes
*/
/******************************/
/* total number of interrupts */
unsigned int ints;
/* software monitoring hw errors */
unsigned int tx_buf_error;
/* Software fifo overrun */
unsigned int rx_sw_dovr;
} occan_stats;
/* indexes into occan_stats.err_bus_segs[index] */
#define OCCAN_SEG_ID28 0x02 /* ID field bit 28:21 */
#define OCCAN_SEG_ID20 0x06 /* ID field bit 20:18 */
#define OCCAN_SEG_ID17 0x07 /* ID field bit 17:13 */
#define OCCAN_SEG_ID12 0x0f /* ID field bit 12:5 */
#define OCCAN_SEG_ID4 0x0e /* ID field bit 4:0 */
#define OCCAN_SEG_START 0x03 /* Start of Frame */
#define OCCAN_SEG_SRTR 0x04 /* Bit SRTR */
#define OCCAN_SEG_IDE 0x05 /* Bit IDE */
#define OCCAN_SEG_RTR 0x0c /* Bit RTR */
#define OCCAN_SEG_RSV0 0x09 /* Reserved bit 0 */
#define OCCAN_SEG_RSV1 0x0d /* Reserved bit 1 */
#define OCCAN_SEG_DLEN 0x0b /* Data Length code */
#define OCCAN_SEG_DFIELD 0x0a /* Data Field */
#define OCCAN_SEG_CRC_SEQ 0x08 /* CRC Sequence */
#define OCCAN_SEG_CRC_DELIM 0x18 /* CRC Delimiter */
#define OCCAN_SEG_ACK_SLOT 0x19 /* Acknowledge slot */
#define OCCAN_SEG_ACK_DELIM 0x1b /* Acknowledge delimiter */
#define OCCAN_SEG_EOF 0x1a /* End Of Frame */
#define OCCAN_SEG_INTERMISSION 0x12 /* Intermission */
#define OCCAN_SEG_ACT_ERR 0x11 /* Active error flag */
#define OCCAN_SEG_PASS_ERR 0x16 /* Passive error flag */
#define OCCAN_SEG_DOMINANT 0x13 /* Tolerate dominant bits */
#define OCCAN_SEG_EDELIM 0x17 /* Error delimiter */
#define OCCAN_SEG_OVERLOAD 0x1c /* overload flag */
#define CANMSG_OPT_RTR 0x40 /* RTR Frame */
#define CANMSG_OPT_EXTENDED 0x80 /* Exteneded frame */
#define CANMSG_OPT_SSHOT 0x01 /* Single Shot, no retry */
#define OCCAN_IOC_START 1
#define OCCAN_IOC_STOP 2
#define OCCAN_IOC_GET_CONF 3
#define OCCAN_IOC_GET_STATS 4
#define OCCAN_IOC_GET_STATUS 5
#define OCCAN_IOC_SET_SPEED 6
#define OCCAN_IOC_SPEED_AUTO 7
#define OCCAN_IOC_SET_LINK 8
#define OCCAN_IOC_SET_FILTER 9
#define OCCAN_IOC_SET_BLK_MODE 10
#define OCCAN_IOC_SET_BUFLEN 11
#define OCCAN_IOC_SET_BTRS 12
struct occan_afilter {
unsigned char code[4];
unsigned char mask[4];
int single_mode;
};
#define OCCAN_STATUS_RESET 0x01
#define OCCAN_STATUS_OVERRUN 0x02
#define OCCAN_STATUS_WARN 0x04
#define OCCAN_STATUS_ERR_PASSIVE 0x08
#define OCCAN_STATUS_ERR_BUSOFF 0x10
#define OCCAN_STATUS_QUEUE_ERROR 0x80
#define OCCAN_BLK_MODE_RX 0x1
#define OCCAN_BLK_MODE_TX 0x2
void occan_register_drv (void);
#define OCCAN_SPEED_500K 500000
#define OCCAN_SPEED_250K 250000
#define OCCAN_SPEED_125K 125000
#define OCCAN_SPEED_75K 75000
#define OCCAN_SPEED_50K 50000
#define OCCAN_SPEED_25K 25000
#define OCCAN_SPEED_10K 10000
#ifdef __cplusplus
}
#endif
#endif
/*
* Header file for RTEMS SATCAN FPGA driver
*
* COPYRIGHT (c) 2009.
* Cobham Gaisler AB.
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*/
#ifndef __SATCAN_H__
#define __SATCAN_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Config structure passed to SatCAN_init(..) */
typedef struct {
/* Configuration */
int nodeno;
int dps;
/* Callback functions */
void (*ahb_irq_callback)(void);
void (*pps_irq_callback)(void);
void (*m5_irq_callback)(void);
void (*m4_irq_callback)(void);
void (*m3_irq_callback)(void);
void (*m2_irq_callback)(void);
void (*m1_irq_callback)(void);
void (*sync_irq_callback)(void);
void (*can_irq_callback)(unsigned int fifo);
} satcan_config;
#define SATCAN_HEADER_SIZE 4
#define SATCAN_HEADER_NMM_POS 3
#define SATCAN_PAYLOAD_SIZE 8
/* SatCAN message */
typedef struct {
unsigned char header[SATCAN_HEADER_SIZE]; /* Header of SatCAN message */
unsigned char payload[SATCAN_PAYLOAD_SIZE]; /* Payload of SatCAN message */
} satcan_msg;
/* SatCAN modify register structure */
typedef struct {
unsigned int reg;
unsigned int val;
} satcan_regmod;
/* Driver interface */
int satcan_register(satcan_config *conf);
/* SatCAN interrupt IDs */
#define SATCAN_IRQ_NONACT_TO_ACT 0
#define SATCAN_IRQ_ACTIVE_TO_NONACT 1
#define SATCAN_IRQ_STR1_TO_DPS 2
#define SATCAN_IRQ_DPS_TO_STR1 3
#define SATCAN_IRQ_STR2_TO_DPS 4
#define SATCAN_IRQ_DPS_TO_STR2 5
#define SATCAN_IRQ_STR3_TO_DPS 6
#define SATCAN_IRQ_DPS_TO_STR3 7
#define SATCAN_IRQ_PLD1_TO_DPS 8
#define SATCAN_IRQ_DPS_TO_PLD1 9
#define SATCAN_IRQ_PLD2_TO_DPS 10
#define SATCAN_IRQ_DPS_TO_PLD2 11
#define SATCAN_IRQ_SYNC 16
#define SATCAN_IRQ_TIME_MARKER1 17
#define SATCAN_IRQ_TIME_MARKER2 18
#define SATCAN_IRQ_TIME_MARKER3 19
#define SATCAN_IRQ_TIME_MARKER4 20
#define SATCAN_IRQ_TIME_MARKER5 21
#define SATCAN_IRQ_EOD1 22
#define SATCAN_IRQ_EOD2 23
#define SATCAN_IRQ_TOD 24
#define SATCAN_IRQ_CRITICAL 25
/* IOC */
#define SATCAN_IOC_DMA_2K 1 /* Use DMA area for 2K messages */
#define SATCAN_IOC_DMA_8K 2 /* Use DMA area for 8K messages */
#define SATCAN_IOC_GET_REG 3 /* Provides direct read access to all core registers */
#define SATCAN_IOC_SET_REG 4 /* Provides direct write access to all core registers */
#define SATCAN_IOC_OR_REG 5 /* Provides direct read access to all core registers */
#define SATCAN_IOC_AND_REG 6 /* Provides direct write access to all core registers */
#define SATCAN_IOC_EN_TX1_DIS_TX2 7 /* Enable DMA TX channel 1, Disable DMA TX channel 2 */
#define SATCAN_IOC_EN_TX2_DIS_TX1 8 /* Enable DMA TX channel 2, Disable DMA TX channel 1 */
#define SATCAN_IOC_GET_DMA_MODE 9 /* Returns the current DMA mode */
#define SATCAN_IOC_SET_DMA_MODE 10 /* Sets the DMA mode */
#define SATCAN_IOC_ACTIVATE_DMA 11 /* Directly activate DMA channel */
#define SATCAN_IOC_DEACTIVATE_DMA 12 /* Directly deactivate DMA channel */
#define SATCAN_IOC_DMA_STATUS 13 /* Returns status of directly activated DMA */
#define SATCAN_IOC_GET_DOFFSET 14 /* Get TX DMA offset */
#define SATCAN_IOC_SET_DOFFSET 15 /* Set TX DMA offset */
#define SATCAN_IOC_GET_TIMEOUT 16 /* Set TX DMA timeout */
#define SATCAN_IOC_SET_TIMEOUT 17 /* Get TX DMA timeout */
/* Values used to select core register with IOC_SET_REG/IOC_GET_REG */
#define SATCAN_SWRES 0 /* Software reset */
#define SATCAN_INT_EN 1 /* Interrupt enable */
#define SATCAN_FIFO 3 /* FIFO read */
#define SATCAN_FIFO_RES 4 /* FIFO reset */
#define SATCAN_TSTAMP 5 /* Current time stamp */
#define SATCAN_CMD0 6 /* Command register 0 */
#define SATCAN_CMD1 7 /* Command register 1 */
#define SATCAN_START_CTC 8 /* Start cycle time counter */
#define SATCAN_RAM_BASE 9 /* RAM offset address */
#define SATCAN_STOP_CTC 10 /* Stop cycle time counter / DPS active status */
#define SATCAN_DPS_ACT 10 /* Stop cycle time counter / DPS active status */
#define SATCAN_PLL_RST 11 /* DPLL reset */
#define SATCAN_PLL_CMD 12 /* DPLL command */
#define SATCAN_PLL_STAT 13 /* DPLL status */
#define SATCAN_PLL_OFF 14 /* DPLL offset */
#define SATCAN_DMA 15 /* DMA channel enable */
#define SATCAN_DMA_TX_1_CUR 16 /* DMA channel 1 TX current address */
#define SATCAN_DMA_TX_1_END 17 /* DMA channel 1 TX end address */
#define SATCAN_DMA_TX_2_CUR 18 /* DMA channel 2 TX current address */
#define SATCAN_DMA_TX_2_END 19 /* DMA channel 2 TX end address */
#define SATCAN_RX 20 /* CAN RX enable / Filter start ID */
#define SATCAN_FILTER_START 20 /* CAN RX enable / Filter start ID */
#define SATCAN_FILTER_SETUP 21 /* Filter setup / Filter stop ID */
#define SATCAN_FILTER_STOP 21 /* Filter setup / Filter stop ID */
#define SATCAN_WCTRL 32 /* Wrapper status/control register */
#define SATCAN_WIPEND 33 /* Wrapper interrupt pending register */
#define SATCAN_WIMASK 34 /* Wrapper interrupt mask register */
#define SATCAN_WAHBADDR 35 /* Wrapper AHB address register */
/* Values used to communicate DMA mode */
#define SATCAN_DMA_MODE_USER 0
#define SATCAN_DMA_MODE_SYSTEM 1
/* Values used to directly activate DMA channel */
#define SATCAN_DMA_ENABLE_TX1 1
#define SATCAN_DMA_ENABLE_TX2 2
#ifdef __cplusplus
}
#endif
#endif /* __SATCAN_H__ */
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