+add: Further basic benchmark circuits whcih address particular architectural features.

circuits/basic/basic_adder/benchmarkSettings.json

+{
+    "name" : "Basic Adder",
+    "genericSettings" : {
+	"./hdl/basic_adder.vhd" : {
+            "INPUT_WIDTH" : [8, 16],
+            "INPUT_REG"   : true, 
+            "OUTPUT_REG"  : true
+	}
+    },
+    "useDevices" : {
+	"Virtex-5QV" : {"ISE" : "13.2"}
+    }
+}

circuits/basic/basic_adder/benchmark_basic_adder.py

+#!/usr/bin/env python
+
+#import modules
+
+import sys
+sys.path.insert(0, '../../../benchmark_env')
+
+import benchmark
+
+# setup benchmark
+
+prjSettings       = './prjSettings.json'
+benchmarkSettings = './benchmarkSettings.json'
+outputEnable      = False
+
+bench = benchmark.Benchmark(prjSettings, benchmarkSettings)
+
+
+# start benchmark and print results
+
+bench.start()
+bench.printResults()

circuits/basic/basic_adder/hdl/basic_adder.vhd

+-------------------------------------------------------------------------------
+-- Title      : Basic Adder Circuit
+-- Project    : ESA FPGA Benchmark Suite
+-------------------------------------------------------------------------------
+-- File       : basic_adder.vhd
+-- Author     : Thomas Lange  <Thomas.Lange@esa.int>
+-- Company    : TEC-EDM ESTEC/ESA
+-- Created    : 2015-10-07
+-- Last update: 2016-07-26
+-- Platform   : 
+-- Standard   : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description: Two signed input adder circuit with generic input width.
+--      Implementation utilises the numeric_std package.
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author  Description
+-- 2015-10-07  1.0      Thomas Lange    Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.utils.all;
+
+-------------------------------------------------------------------------------
+
+entity basic_adder is
+
+  generic (
+    INPUT_WIDTH : natural := 1;
+
+    INPUT_REG  : boolean := true;
+    OUTPUT_REG : boolean := true
+    );
+
+  port (
+    clk    : in std_logic;
+    nreset : in std_logic;
+
+    in_A : in std_logic_vector(INPUT_WIDTH-1 downto 0);
+    in_B : in std_logic_vector(INPUT_WIDTH-1 downto 0);
+
+    out_sum : out std_logic_vector(INPUT_WIDTH-1 downto 0)
+    );
+
+end entity basic_adder;
+
+-------------------------------------------------------------------------------
+
+architecture basic_adder_arch of basic_adder is
+
+  -- resulting output width
+  constant OUTPUT_WIDTH : natural := INPUT_WIDTH;
+
+  -----------------------------------------------------------------------------
+  -- Internal signal declarations
+  -----------------------------------------------------------------------------
+
+  -- I/O register signals
+  signal A_reg, B_reg : std_logic_vector(INPUT_WIDTH-1 downto 0);
+  signal sum_reg      : std_logic_vector(OUTPUT_WIDTH-1 downto 0);
+
+  -- adder signals
+  signal A, B    : signed(INPUT_WIDTH-1 downto 0);
+  signal sum     : signed(OUTPUT_WIDTH-1 downto 0);
+  signal sum_slv : std_logic_vector(OUTPUT_WIDTH-1 downto 0);
+  
+begin  -- architecture basic_adder_arch
+
+  -----------------------------------------------------------------------------
+  -- Register input values (if enabled)
+  -----------------------------------------------------------------------------
+
+  reg_A : io_reg
+    generic map(INPUT_REG)
+    port map (clk, nreset, '1', in_A, A_reg);
+
+  reg_B : io_reg
+    generic map(INPUT_REG)
+    port map (clk, nreset, '1', in_B, B_reg);
+
+
+
+  -----------------------------------------------------------------------------
+  -- Adder description
+  -----------------------------------------------------------------------------
+
+  A <= signed(A_reg);
+  B <= signed(B_reg);
+
+  sum <= A + B;
+
+
+
+  -----------------------------------------------------------------------------
+  -- Register output values (if enabled)
+  -----------------------------------------------------------------------------
+
+  sum_slv <= std_logic_vector(sum);
+
+  reg_sum : io_reg
+    generic map(OUTPUT_REG)
+    port map (clk, nreset, '1', sum_slv, sum_reg);
+
+  -- assign output value
+  out_sum <= sum_reg;
+
+end architecture basic_adder_arch;
+
+-------------------------------------------------------------------------------

circuits/basic/basic_adder/prjSettings.json

+{
+    "name": "basic_adder",
+    "hdlFiles": [
+	"../../utils/hdl/io_ff.vhd",
+	"../../utils/hdl/io_reg.vhd",
+	"../../utils/hdl/utils.vhd",
+	"./hdl/basic_adder.vhd"
+    ],
+    "vhdlVersion": "VHDL1993"
+}

circuits/basic/basic_mult/benchmarkSettings.json

+{
+    "name" : "Basic Multiplier",
+    "genericSettings" : {
+	"./hdl/basic_mult.vhd" : {
+            "INPUT_WIDTH" : [8, 16],
+            "INPUT_REG"  : true, 
+            "OUTPUT_REG" : true
+	}
+    },
+    "useDevices" : {
+	"Virtex-5QV" : {"ISE" : "13.2"}
+    }
+}

circuits/basic/basic_mult/benchmark_basic_mult.vhd

+#!/usr/bin/env python
+
+#import modules
+
+import sys
+sys.path.insert(0, '../../../benchmark_env')
+
+import benchmark
+
+# setup benchmark
+
+prjSettings       = './prjSettings.json'
+benchmarkSettings = './benchmarkSettings.json'
+outputEnable      = False
+
+bench = benchmark.Benchmark(prjSettings, benchmarkSettings)
+
+
+# start benchmark and print results
+
+bench.start()
+bench.printResults()

circuits/basic/basic_mult/hdl/basic_mult.vhd

+-------------------------------------------------------------------------------
+-- Title      : Generic Multiplier
+-- Project    : ESA FPGA Benchmark Suite
+-------------------------------------------------------------------------------
+-- File       : basic_mult.vhd
+-- Author     : Thomas Lange  <Thomas.Lange@esa.int>
+-- Company    : TEC-EDM ESTEC/ESA
+-- Created    : 2015-11-17
+-- Last update: 2015-11-17
+-- Platform   : 
+-- Standard   : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description: Two signed input multiplier with generic input width.
+--      Implementation utilises the numeric_std package.
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author  Description
+-- 2015-10-12  1.0      Thomas Lange    Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.utils.all;
+
+-------------------------------------------------------------------------------
+
+entity basic_mult is
+
+  generic (
+    INPUT_WIDTH : natural := 16;
+
+    INPUT_REG  : boolean := false;
+    OUTPUT_REG : boolean := false
+    );
+
+  port (
+    clk    : in std_logic;
+    nreset : in std_logic;
+
+    in_A : in std_logic_vector(INPUT_WIDTH-1 downto 0);
+    in_B : in std_logic_vector(INPUT_WIDTH-1 downto 0);
+
+    out_prod : out std_logic_vector(2*INPUT_WIDTH-1 downto 0)
+    );
+
+end entity basic_mult;
+
+-------------------------------------------------------------------------------
+
+architecture basic_mult_arch of basic_mult is
+
+  -- resulting output width
+  constant OUTPUT_WIDTH : natural := 2*INPUT_WIDTH;
+
+  -----------------------------------------------------------------------------
+  -- Internal signal declarations
+  -----------------------------------------------------------------------------
+
+  -- I/O register signals
+  signal A_reg, B_reg : std_logic_vector(INPUT_WIDTH-1 downto 0);
+  signal prod_reg     : std_logic_vector(OUTPUT_WIDTH-1 downto 0);
+
+  -- adder signals
+  signal A, B     : signed(INPUT_WIDTH-1 downto 0);
+  signal prod     : signed(OUTPUT_WIDTH-1 downto 0);
+  signal prod_slv : std_logic_vector(OUTPUT_WIDTH-1 downto 0);
+  
+begin  -- architecture basic_mult_arch
+
+  -----------------------------------------------------------------------------
+  -- Register input values (if enabled)
+  -----------------------------------------------------------------------------
+
+  reg_A : io_reg
+    generic map(INPUT_REG)
+    port map (clk, nreset, '1', in_A, A_reg);
+
+  reg_B : io_reg
+    generic map(INPUT_REG)
+    port map (clk, nreset, '1', in_B, B_reg);
+
+
+
+  -----------------------------------------------------------------------------
+  -- Multiplier description
+  -----------------------------------------------------------------------------
+
+  A <= signed(A_reg);
+  B <= signed(B_reg);
+
+  prod <= A*B;
+
+
+
+  -----------------------------------------------------------------------------
+  -- Register output values (if enabled)
+  -----------------------------------------------------------------------------
+
+  prod_slv <= std_logic_vector(prod);
+  
+  reg_prod : io_reg
+    generic map(OUTPUT_REG)
+    port map (clk, nreset, '1', prod_slv, prod_reg);
+
+  -- assign output value
+  out_prod <= prod_reg;
+
+end architecture basic_mult_arch;
+
+-------------------------------------------------------------------------------

circuits/basic/basic_mult/prjSettings.json

+{
+    "name": "basic_mult",
+    "hdlFiles": [
+	"../../utils/hdl/io_ff.vhd",
+	"../../utils/hdl/io_reg.vhd",
+	"../../utils/hdl/utils.vhd",
+	"./hdl/basic_mult.vhd"
+    ],
+    "vhdlVersion": "VHDL1993"
+}

circuits/basic/generic_compare/benchmarkSettings.json

+{
+    "name" : "Generic Compare",
+    "genericSettings" : {
+	"./hdl/generic_compare.vhd" : {
+            "INPUT_WIDTH"      : [8, 16],
+             "COMPARISON_TYPE" : ["=", "/=", "<", ">", "<=", ">="],
+            "INPUT_REG"  : true, 
+            "OUTPUT_REG" : true
+	}
+    },
+    "useDevices" : {
+	"Virtex-5QV" : {"ISE" : "13.2"}
+    }
+}

circuits/basic/generic_compare/benchmark_generic_compare.py

+#!/usr/bin/env python
+
+#import modules
+
+import sys
+sys.path.insert(0, '../../../benchmark_env')
+
+import benchmark
+
+# setup benchmark
+
+prjSettings       = './prjSettings.json'
+benchmarkSettings = './benchmarkSettings.json'
+outputEnable      = False
+
+bench = benchmark.Benchmark(prjSettings, benchmarkSettings)
+
+
+# start benchmark and print results
+
+bench.start()
+bench.printResults()

circuits/basic/generic_compare/hdl/generic_compare.vhd

+-------------------------------------------------------------------------------
+-- Title      : Comparison 
+-- Project    : ESA FPGA Benchmark Suite
+-------------------------------------------------------------------------------
+-- File       : generic_compare.vhd
+-- Author     : Thomas Lange  <Thomas.Lange@esa.int>
+-- Company    : TEC-EDM ESTEC/ESA
+-- Created    : 2015-12-09
+-- Last update: 2016-06-09
+-- Platform   : 
+-- Standard   : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description: Compare two signals (=, /=, <, >, <=, >=) with generic input
+--      width and generic input and output register.
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author  Description
+-- 2015-12-09  1.0      Thomas Lange    Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.utils.all;
+
+-------------------------------------------------------------------------------
+
+entity generic_compare is
+
+  generic (
+    INPUT_WIDTH     : natural := 16;
+    COMPARISON_TYPE : string  := ">";   -- set the comparision type
+                                        -- (=, /=, <, >, <=, >=)
+
+    INPUT_REG  : boolean := false;
+    OUTPUT_REG : boolean := false
+    );
+
+  port (
+    clk    : in std_logic;
+    nreset : in std_logic;
+
+    in_A            : in  std_logic_vector(INPUT_WIDTH-1 downto 0);
+    in_B            : in  std_logic_vector(INPUT_WIDTH-1 downto 0);
+    out_compare_res : out std_logic
+    );
+
+end entity generic_compare;
+
+-------------------------------------------------------------------------------
+
+architecture generic_compare_arch of generic_compare is
+
+  -----------------------------------------------------------------------------
+  -- Internal signal declarations
+  -----------------------------------------------------------------------------
+
+  -- I/O register signals
+  signal A_reg, B_reg    : std_logic_vector(INPUT_WIDTH-1 downto 0);
+  signal compare_res_reg : std_logic;
+
+  -- adder signals
+  signal A, B        : signed(INPUT_WIDTH-1 downto 0);
+  signal compare_res : std_logic;
+  
+begin  -- architecture generic_compare_arch
+
+  -----------------------------------------------------------------------------
+  -- Register input values (if enabled)
+  -----------------------------------------------------------------------------
+
+  reg_A : io_reg
+    generic map(INPUT_REG)
+    port map (clk, nreset, '1', in_A, A_reg);
+
+  reg_B : io_reg
+    generic map(INPUT_REG)
+    port map (clk, nreset, '1', in_B, B_reg);
+
+
+
+  -----------------------------------------------------------------------------
+  -- Multiplier description
+  -----------------------------------------------------------------------------
+
+  A <= signed(A_reg);
+  B <= signed(B_reg);
+
+  -- compare if the input signals are eqaul
+  compare_equal : if COMPARISON_TYPE = "=" or
+                    COMPARISON_TYPE = "= " generate
+    compare_res <= '1' when A = B else
+                   '0';
+  end generate compare_equal;
+
+  -- compare if the input signals are uneqaul
+  compare_unequal : if COMPARISON_TYPE = "/=" generate
+    compare_res <= '1' when A /= B else
+                   '0';
+  end generate compare_unequal;
+
+  -- compare if the A is less than B
+  compare_less_than : if COMPARISON_TYPE = "<" or
+                        COMPARISON_TYPE = "< " generate
+    compare_res <= '1' when A < B else
+                   '0';
+  end generate compare_less_than;
+
+  -- compare if the A is greater than B
+  compare_greater_than : if COMPARISON_TYPE = ">" or
+                           COMPARISON_TYPE = "> " generate
+    compare_res <= '1' when A > B else
+                   '0';
+  end generate compare_greater_than;
+
+  -- compare if the A is less or equal B
+  compare_less_or_equal : if COMPARISON_TYPE = "<=" generate
+    compare_res <= '1' when A <= B else
+                   '0';
+  end generate compare_less_or_equal;
+
+  -- compare if the A is greater or equal B
+  compare_greater_or_equal : if COMPARISON_TYPE = ">=" generate
+    compare_res <= '1' when A >= B else
+                   '0';
+  end generate compare_greater_or_equal;
+
+
+
+  -----------------------------------------------------------------------------
+  -- Register output values (if enabled)
+  -----------------------------------------------------------------------------
+
+  reg_compare_res : io_ff
+    generic map(OUTPUT_REG)
+    port map (clk, nreset, '1', compare_res, compare_res_reg);
+
+  -- assign output value
+  out_compare_res <= compare_res_reg;
+  
+end architecture generic_compare_arch;
+
+-------------------------------------------------------------------------------

circuits/basic/generic_compare/prjSettings.json

+{
+    "name": "generic_compare",
+    "hdlFiles": [
+	"../../utils/hdl/io_ff.vhd",
+	"../../utils/hdl/io_reg.vhd",
+	"../../utils/hdl/utils.vhd",
+	"./hdl/generic_compare.vhd"
+    ],
+    "vhdlVersion": "VHDL1993"
+}

circuits/basic/generic_ram/benchmarkSettings.json

+{
+    "name" : "Generic RAM",
+    "genericSettings" : {
+	"./hdl/generic_ram.vhd" : {
+            "ADDR_WIDTH" : [8, 16],
+            "DATA_WIDTH" : [8, 16],
+            "INPUT_REG"  : true, 
+            "OUTPUT_REG" : true
+	}
+    },
+    "useDevices" : {
+	"Virtex-5QV" : {"ISE" : "13.2"}
+    }
+}

circuits/basic/generic_ram/benchmark_generic_ram.py

+#!/usr/bin/env python
+
+#import modules
+
+import sys
+sys.path.insert(0, '../../../benchmark_env')
+
+import benchmark
+
+# setup benchmark
+
+prjSettings       = './prjSettings.json'
+benchmarkSettings = './benchmarkSettings.json'
+outputEnable      = False
+
+bench = benchmark.Benchmark(prjSettings, benchmarkSettings)
+
+
+# start benchmark and print results
+
+bench.start()
+bench.printResults()

circuits/basic/generic_ram/hdl/generic_ram.vhd

+-------------------------------------------------------------------------------
+-- Title      : Generic RAM
+-- Project    : ESA FPGA Benchmark Suite
+-------------------------------------------------------------------------------
+-- File       : generic_ram.vhd
+-- Author     : Thomas Lange  <Thomas.Lange@esa.int>
+-- Company    : TEC-EDM ESTEC/ESA
+-- Created    : 2015-11-04
+-- Last update: 2016-07-28
+-- Platform   : 
+-- Standard   : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description: RAM description with generic depth and word width.
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author  Description
+-- 2015-11-04  1.0      Thomas Lange    Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.utils.all;
+
+-------------------------------------------------------------------------------
+
+entity generic_ram is
+
+  generic (
+    ADDR_WIDTH : natural := 16;
+    DATA_WIDTH : natural := 8;
+    INPUT_REG : boolean := True;
+    OUTPUT_REG : boolean := True
+    );
+
+
+