*fix: read out of VHDL version entry.

tools/xilinx/new_ise_project.tcl

@@ -55,7 +55,7 @@ set prj_set [json::json2dict $prj_set_json]
 set project_name [dict get $prj_set name]
 set hdl_files [dict get $prj_set hdlFiles]
 if { [dict exists $prj_set VHDLVersion] == 1} {
-    set VHDL_ver [dict get $prj_set VHDLVersion]
+    set VHDL_ver [dict get $prj_set vhdlVersion]
 } else {
     set VHDL_ver "VHDL1993"
 }