generic_ram.vhd 3.99 KB
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-------------------------------------------------------------------------------
-- Title      : Generic RAM
-- Project    : ESA FPGA Benchmark Suite
-------------------------------------------------------------------------------
-- File       : generic_ram.vhd
-- Author     : Thomas Lange  <Thomas.Lange@esa.int>
-- Company    : TEC-EDM ESTEC/ESA
-- Created    : 2015-11-04
-- Last update: 2016-07-28
-- Platform   : 
-- Standard   : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: RAM description with generic depth and word width.
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2015-11-04  1.0      Thomas Lange    Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library work;
use work.utils.all;

-------------------------------------------------------------------------------

entity generic_ram is

  generic (
    ADDR_WIDTH : natural := 16;
    DATA_WIDTH : natural := 8;
    INPUT_REG : boolean := True;
    OUTPUT_REG : boolean := True
    );



  port (
    clk    : in std_logic;
    nreset : in std_logic;

    in_we   : in std_logic;
    in_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
    in_data : in std_logic_vector(DATA_WIDTH-1 downto 0);

    out_data : out std_logic_vector(DATA_WIDTH-1 downto 0)
    );

end entity generic_ram;

-------------------------------------------------------------------------------

architecture generic_ram_arch of generic_ram is

  -----------------------------------------------------------------------------
  -- Internal signal declarations
  -----------------------------------------------------------------------------

  type mem is array(natural range <>) of std_logic_vector(DATA_WIDTH-1 downto 0);
  signal ram_block : mem(0 to 2**ADDR_WIDTH-1);

  signal we_reg                    : std_logic;
  signal addr_reg                  : std_logic_vector(ADDR_WIDTH-1 downto 0);
  signal data_in_reg, data_out_reg : std_logic_vector(DATA_WIDTH-1 downto 0);

  signal we                    : std_logic;
  signal read_addr, write_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
  signal data, q               : std_logic_vector(DATA_WIDTH-1 downto 0);
  
begin  -- architecture generic_ram_arch


  -----------------------------------------------------------------------------
  -- Register input values (if enabled)
  -----------------------------------------------------------------------------

  reg_we : io_ff
    generic map(INPUT_REG)
    port map (clk, nreset, '1', in_we, we_reg);

  reg_addr : io_reg
    generic map(INPUT_REG)
    port map (clk, nreset, '1', in_addr, addr_reg);

  reg_data_in : io_reg
    generic map(INPUT_REG)
    port map (clk, nreset, '1', in_data, data_in_reg);
  
  we <= we_reg;

  read_addr  <= addr_reg;
  write_addr <= addr_reg;

  data <= data_in_reg;



  -----------------------------------------------------------------------------
  -- RAM Description
  -----------------------------------------------------------------------------

  ram : process (clk, nreset) is
  begin  -- process ram
    if nreset = '0' then                -- asynchronous reset (active low)
      ram_block <= (others => (others => '0'));
    elsif clk'event and clk = '1' then  -- rising clock edge
      if we = '1' then
        ram_block(to_integer(unsigned(write_addr))) <= data;
      end if;
    end if;
  end process ram;

  q <= ram_block(to_integer(unsigned(read_addr)));



  -----------------------------------------------------------------------------
  -- Register and assign output values (if enabled)
  -----------------------------------------------------------------------------

  reg_data_out : io_reg
    generic map(OUTPUT_REG)
    port map (clk, nreset, '1', q, data_out_reg);
  
  out_data <= data_out_reg;

end architecture generic_ram_arch;

-------------------------------------------------------------------------------